section 7 - Index of

cycles that may be required over and above those needed for the basic MACR instructiondue to the parallel move portion of the instruction.2. Evaluate the "mv" term using Table A-7.The parallel move portion of the MACR instruction consists of an XV memory move.According to Table A-7, the parallel move portion of the instruction will require mv=Oadditional instruction program words and mv=(ea+axy) additional oscillator clock cycles.The term "ea" represents the number of additional (if any) oscillator clock cycles that arerequired for the effective addressing move specified in the parallel move portion of theinstruction. The term "axy" represents the number of additional (if any) oscillator clockcycles that are required to access an XV memory operand.3. Evaluate the "ea" term using Table A-13.The parallel move portion of the MACR instruction consists of an XV memory movewhich uses both address register banks (RO-R3 and R4-R7) in generating the effectiveaddresses of the XV memory operands. Thus, the two effective address operationsoccur in parallel, and the larger of the two "ea" terms should be used. The X memorymove operation uses the "postdecrement by 1" effective addressing mode. According toTable A-13, this operation will require ea=O additional oscillator clock cycles. The Vmemory move operation uses the "postincrement by 1" effective addressing mode.According to Table A-13, this operation will also require ea=O additional oscillator clockcycles. Thus, using the maximum value of "ea", the effective addressing modes used inthe parallel move portion of the MACR instruction will require ea=O additional oscillatorclock cycles.4. Evaluate the "axy" term using Table A-14.-The parallel move portion of the MACR instruction consists of an XV memory move.According to Table A-14, the term "axy" depends upon where the referenced X and Vmemory locations are located in the DSP56K memory space. External memoryaccesses require additional oscillator clock cycles according to the number of wait statesprogrammed into the DSP56K bus control register (SCR). Thus, assuming that the 16-bitbus control register contains the value $1135, external X memory accesses require wx=1wait state of additional oscillator clock cycle while external Y memory accesses requirewy=1 wait state or additional oscillator clock cycle. For this example, the X memory referenceis assumed to be an Internal reference; the V memory reference is assumed to bean external reference. Thus, according to Table A-14, the XV memory reference in theparallel move portion of the MACR instruction will require axy=wy=1 additional oscillatorclock cycle.