section 7 - Index of
section 7 - Index of section 7 - Index of
WAIT Wait for Interrupt WAITOperation:Disable clocks to the processor core andenter the WAIT processing state.Assembler Syntax:WAITDescription: Enter the WAIT processing state. The internal clocks to the processor coreand memories are gated off, and all activity in the processor is suspended until anunmasked interrupt occurs. The clock oscillator and the internal I/O peripheral clocksremain active. If WAIT is executed when an interrupt is pending, the interrupt will be processed;the effect will be the same as if the processor never entered the WAIT state andthree NOPs followed the WAIT instruction. When an unmasked interrupt or external(hardware) processor RESET occurs, the processor leaves the WAIT state and be,ginsexception processing of the unmasked interrupt or RESET condition. The BRlBG circuitsremain active during the WAIT state. The WAIT state is a low-power standby state. Theprocessor always leaves the WAIT state in the T2 clock phase (see the DSP56001Advance Information Data Sheet (ADI1290)). Therefore, multiple processors may besynchronized by having them all enter the WAIT state and then interrupting them with acommon interrupt.Restrictions: A WAIT instruction cannot be used in a fast interrupt routine.A WAIT instruction cannot be the last instruction in a DO loop (at LA).A WAIT instruction cannot be repeated using the REP instruction.Example:WAIT;enter low power mode, wait for interruptExplanation of Example: The WAIT instruction suspends normal instruction executionand waits for an unmasked interrupt or external RESET to occur.
WAIT Wait for Interrupt WAITCondition Codes:I LF I OM I T I ** I S1 I SO I 11 I 10 I s I L E I u N I zGGR15 14 13 12 11 10 9 8 7 6 5 4 3 2 oThe condition codes are not affected by this instruction.Instruction Format:WAITOpcode:23 16 15 87010 0 0 0 0 0 0 0100 0 0 0 00 01100001101Instruction Fields:NoneTiming: The WAIT instruction takes a minimum of 16 cycles to execute when an internalinterrupt is pending during the execution of the WAIT instructionMemory: 1 program word-
- Page 481 and 482: NORM Normalize Accumulator Iteratio
- Page 483 and 484: NOTLogical ComplementNOTInstruction
- Page 485 and 486: ORLogical Inclusive ORORInstruction
- Page 487 and 488: ORI OR Immediate with Control Regis
- Page 489 and 490: REP Repeat Next Instruction REPRest
- Page 491 and 492: REPRepeat Next InstructionREPInstru
- Page 493 and 494: REPRepeat Next InstructionREPInstru
- Page 495 and 496: REP Repeat Next Instruction REPNote
- Page 497 and 498: RESETReset On-Chip Peripheral Devic
- Page 499 and 500: RND Round Accumulator RNDConvergent
- Page 501 and 502: RNDRound AccumulatorRNDInstruction
- Page 503 and 504: ROL Rotate Left ROLCondition Codes:
- Page 505 and 506: ROR Rotate Right RORCondition Codes
- Page 507 and 508: RTIReturn from InterruptRTIConditio
- Page 509 and 510: RTSReturn from SubroutineRTSInstruc
- Page 511 and 512: sec Subtract Long with Carry secExp
- Page 513 and 514: secSubtract Long with CarrysecInstr
- Page 515 and 516: STOPStop Instruction ProcessingSTOP
- Page 517 and 518: SUB Subtract SUBCondition Codes:S -
- Page 519 and 520: SUBL Shift Left and Subtract Accumu
- Page 521 and 522: SUBR Shift Right and Subtract Accum
- Page 523 and 524: SWISoftware InterruptSWICondition C
- Page 525 and 526: Tee Transfer Conditionally Teetion
- Page 527 and 528: Tee Transfer Conditionally TeeInstr
- Page 529 and 530: TFR Transfer Data ALU Register TFRC
- Page 531: TSTTest AccumulatorTSTInstruction F
- Page 535 and 536: including the number of words per i
- Page 537 and 538: 5. Compute final results.Thus, base
- Page 539 and 540: JLC (R2+N2)will requireand will exe
- Page 541 and 542: Table A-6 Instruction Timing Summar
- Page 543 and 544: Note that the "ap" term in Table A-
- Page 545 and 546: Table A-14 Memory Access Timing Sum
- Page 547 and 548: Other RestrictionsDO SSH,xxxxJSR to
- Page 549 and 550: Immediately before MOVEC from SSH o
- Page 551 and 552: A.9.S REP RestrictionsThe REP instr
- Page 553 and 554: Table A-18 Triple-Bit Register Enco
- Page 555 and 556: Table A-24 Program Control Unit Reg
- Page 557 and 558: R: Register to Register Parallel Da
- Page 559 and 560: JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
- Page 561 and 562: JSSET#n,S,xxxx23 16 15 87 000001011
- Page 563 and 564: BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
- Page 565 and 566: MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
- Page 567 and 568: LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
- Page 569 and 570: ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
- Page 571 and 572: Table A-28 Operation Code QQQ Decod
- Page 573 and 574: Table A-30 Special Case #10 P E R C
- Page 575 and 576: NEGD23 87 43 0DATA BUS MOVE FIELDLS
- Page 577: ADDRS,D23 87 43 oDATA BUS MOVE FIEL
- Page 580 and 581: lEI
WAIT Wait for Interrupt WAITOperation:Disable clocks to the processor core andenter the WAIT processing state.Assembler Syntax:WAITDescription: Enter the WAIT processing state. The internal clocks to the processor coreand memories are gated <strong>of</strong>f, and all activity in the processor is suspended until anunmasked interrupt occurs. The clock oscillator and the internal I/O peripheral clocksremain active. If WAIT is executed when an interrupt is pending, the interrupt will be processed;the effect will be the same as if the processor never entered the WAIT state andthree NOPs followed the WAIT instruction. When an unmasked interrupt or external(hardware) processor RESET occurs, the processor leaves the WAIT state and be,ginsexception processing <strong>of</strong> the unmasked interrupt or RESET condition. The BRlBG circuitsremain active during the WAIT state. The WAIT state is a low-power standby state. Theprocessor always leaves the WAIT state in the T2 clock phase (see the DSP56001Advance Information Data Sheet (ADI1290)). Therefore, multiple processors may besynchronized by having them all enter the WAIT state and then interrupting them with acommon interrupt.Restrictions: A WAIT instruction cannot be used in a fast interrupt routine.A WAIT instruction cannot be the last instruction in a DO loop (at LA).A WAIT instruction cannot be repeated using the REP instruction.Example:WAIT;enter low power mode, wait for interruptExplanation <strong>of</strong> Example: The WAIT instruction suspends normal instruction executionand waits for an unmasked interrupt or external RESET to occur.