section 7 - Index of

TFR Transfer Data ALU Register TFROperation: .S4D (parallel move)Assembler Syntax:TFR S,D (parallel move)Description: Transfer data from the specified source data ALU register S to the specifieddestination data ALU accumulator D. TFR uses the internal data ALU data paths;thus, data does not pass through the data shifter/limiters. This allows the full 56-bit contentsof one of the accumulators to be transferred into the other accumulator withoutdata shifting and/or limiting. Moreover, since TFR uses the internal data ALU data paths,parallel moves are possible. The TFR instruction only affects the L condition code bitwhich can be set by data limiting associated with the instruction's parallel move operations.Example:TFR A,B A,X1 Y:(R4+N4),YO ;move A to B and X 1 , update YOBefore ExecutionA~I ___ $_O_1:2_3_45_67_:8_9A_B_C_D __ ~After ExecutionA~I ____ $O_1:_23_45_67_:8_9_AB_C_D __ ~B ~I ___ $_FF_:F_F_FF_F_F:F_F_FF_F_F __ ~B~I ____ $O_1:_23_45_67_:8_9_AB_C_D __ ~Explanation of Example: Prior to execution, the 56-bit A accumulator contains thevalue $01 :234567:89ABCD, and the 56-bit B accumulator contains the value$ff:FFFFFF:FFFFFF. The execution of the TFR A,B instruction moves the 56-bit value inthe A accumulator into the 56-bit B accumulator using the internal data ALU data pathswithout any data shifting and/or limiting. The value in the B accumulator would havebeen limited if a MOVE A,B instruction had been used. Note, however, that the parallelmove portion of the TFR instruction does use the data shifter/limiters. Thus, the valuestored in the 24-bit X1 register (not shown) would have been limited in this example.This example illustrates a triple move instruction.