section 7 - Index of
section 7 - Index of section 7 - Index of
SUB Subtract SUBOperation:O-S -4 D (parallel move)Assembler Syntax:SUB S,D (parallel move)Description: Subtract the source operand S from the destination operand 0 and storethe result in the destination operand O. Words (24 bits), long words (48 bits), and accumulators(56 bits) may be subtracted from the destination accumulator.Note: The carry bit is set correctly using word or long-word source operands if the extensionregister of the destination accumulator (A2 or B2) is the sign extension of bit 47 of thedestination accumulator (A or B). The carry bit is always set correctly using accumulatorsource operands.Example:SUB X1 ,A X:(R2)+N2,RO;24.;bit subtract, load RO, update R2Before ExecutionXi 1~ _________ $_OO_O_OO_3 __ ~A 1~ ___ $_OO_:O_OO_05_8_:24_2_42_4 __--'After ExecutionXii ~ _________ $_O_OO_OO_3 __ ~A~I ____ $_OO_:O_OO_05_5_:24_2_42_4 __ ~Explanation of Example: Prior to execution, the 24-bit X1 register contains the value$000003, and the 56-bit A accumulator contains the value $00:000058:242424. TheSUB instruction automatically appends the 24-bit value in the X1 register with 24 LSzeros, sign extends the resulting 48-bit long word to 56 bits, and subtracts the result fromthe 56-bit A accumulator. Thus, 24-bit operands are subtracted from the MSP portion ofA or B (A 1 or B1) because all arithmetic instructions assume a fractional, twos complementdata representation. Note that 24-bit operands can be subtracted from the LSP portionof A or B (AO or BO) by loading the 24-bit operand into XO or YO, forming a 48-bitword by loading X1 or Y1 with the sign extension of XO or YO, and executing a SUB X,Aor SUB Y,A instruction.
SUB Subtract SUBCondition Codes:S -L -E -U -N -Z -V -C -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0I: I OM I T I ** JR 51 I SO I 11 I '~ I: I LIE I U ClR N I z I v I ~ IComputed according to the definition in A.5 CONDITION CODE COMPUTATIONSet if limiting (parallel move) or overflow has occurred in resultSet if the signed integer portion of A or B result is in useSet if A or B result is unnormalizedSet if bit 55 of A or B result is setSet if A or B result equals zeroSet if overflow has occurred in A or B resultSet if a carry (or borrow) occurs from bit 55 of A or B resultNote: The definitions of the E and U bits vary according to the scaling mode being used.Refer to Section A.5 CONDITION CODE COMPUTATION for complete details.Instruction Format:SUB S,DOpcode:23 8 7 4 3DATA BUS MOVE FIELD I 0 J J J I doo 0OPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:S,D J J J dB,A 001 0A,B 001 1X,A 01 00X,B 0 1 01V,A 01 1 0V,B 0 1 1 1S,DJ J J dXO,A 1 000XO,B 1 001VO,A 1 010VO,B 1 0 1 1X1,A 1 100X1,B 1 1 0 1S,DJ J J dV1,A 1 1 1 0V1,B 1 1 1 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words
- Page 465 and 466: MOVEP Move Peripheral Data MOVEPIns
- Page 467 and 468: MOVEP Move Peripheral Data MOVEPIns
- Page 469 and 470: MPY Signed Multiply MPYExplanation
- Page 471 and 472: MPY Signed Multiply MPYInstruction
- Page 473 and 474: MPYR Signed Multiply and Round MPYR
- Page 475 and 476: MPYR Signed Multiply and Round MPYR
- Page 477 and 478: NEGNegate AccumulatorNEGInstruction
- Page 479 and 480: NOPNo OperationNOPInstruction Forma
- Page 481 and 482: NORM Normalize Accumulator Iteratio
- Page 483 and 484: NOTLogical ComplementNOTInstruction
- Page 485 and 486: ORLogical Inclusive ORORInstruction
- Page 487 and 488: ORI OR Immediate with Control Regis
- Page 489 and 490: REP Repeat Next Instruction REPRest
- Page 491 and 492: REPRepeat Next InstructionREPInstru
- Page 493 and 494: REPRepeat Next InstructionREPInstru
- Page 495 and 496: REP Repeat Next Instruction REPNote
- Page 497 and 498: RESETReset On-Chip Peripheral Devic
- Page 499 and 500: RND Round Accumulator RNDConvergent
- Page 501 and 502: RNDRound AccumulatorRNDInstruction
- Page 503 and 504: ROL Rotate Left ROLCondition Codes:
- Page 505 and 506: ROR Rotate Right RORCondition Codes
- Page 507 and 508: RTIReturn from InterruptRTIConditio
- Page 509 and 510: RTSReturn from SubroutineRTSInstruc
- Page 511 and 512: sec Subtract Long with Carry secExp
- Page 513 and 514: secSubtract Long with CarrysecInstr
- Page 515: STOPStop Instruction ProcessingSTOP
- Page 519 and 520: SUBL Shift Left and Subtract Accumu
- Page 521 and 522: SUBR Shift Right and Subtract Accum
- Page 523 and 524: SWISoftware InterruptSWICondition C
- Page 525 and 526: Tee Transfer Conditionally Teetion
- Page 527 and 528: Tee Transfer Conditionally TeeInstr
- Page 529 and 530: TFR Transfer Data ALU Register TFRC
- Page 531 and 532: TSTTest AccumulatorTSTInstruction F
- Page 533 and 534: WAIT Wait for Interrupt WAITConditi
- Page 535 and 536: including the number of words per i
- Page 537 and 538: 5. Compute final results.Thus, base
- Page 539 and 540: JLC (R2+N2)will requireand will exe
- Page 541 and 542: Table A-6 Instruction Timing Summar
- Page 543 and 544: Note that the "ap" term in Table A-
- Page 545 and 546: Table A-14 Memory Access Timing Sum
- Page 547 and 548: Other RestrictionsDO SSH,xxxxJSR to
- Page 549 and 550: Immediately before MOVEC from SSH o
- Page 551 and 552: A.9.S REP RestrictionsThe REP instr
- Page 553 and 554: Table A-18 Triple-Bit Register Enco
- Page 555 and 556: Table A-24 Program Control Unit Reg
- Page 557 and 558: R: Register to Register Parallel Da
- Page 559 and 560: JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
- Page 561 and 562: JSSET#n,S,xxxx23 16 15 87 000001011
- Page 563 and 564: BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
- Page 565 and 566: MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
SUB Subtract SUBCondition Codes:S -L -E -U -N -Z -V -C -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0I: I OM I T I ** JR 51 I SO I 11 I '~ I: I LIE I U ClR N I z I v I ~ IComputed according to the definition in A.5 CONDITION CODE COMPUTATIONSet if limiting (parallel move) or overflow has occurred in resultSet if the signed integer portion <strong>of</strong> A or B result is in useSet if A or B result is unnormalizedSet if bit 55 <strong>of</strong> A or B result is setSet if A or B result equals zeroSet if overflow has occurred in A or B resultSet if a carry (or borrow) occurs from bit 55 <strong>of</strong> A or B resultNote: The definitions <strong>of</strong> the E and U bits vary according to the scaling mode being used.Refer to Section A.5 CONDITION CODE COMPUTATION for complete details.Instruction Format:SUB S,DOpcode:23 8 7 4 3DATA BUS MOVE FIELD I 0 J J J I doo 0OPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:S,D J J J dB,A 001 0A,B 001 1X,A 01 00X,B 0 1 01V,A 01 1 0V,B 0 1 1 1S,DJ J J dXO,A 1 000XO,B 1 001VO,A 1 010VO,B 1 0 1 1X1,A 1 100X1,B 1 1 0 1S,DJ J J dV1,A 1 1 1 0V1,B 1 1 1 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words
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