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REP Repeat Next Instruction REPInstruction Format:REP SOpcode:23 16 15 6 7 o10 0 0 0 0 1 1 o 11 1 d d d d d dl 0 o 1 0 0 0 0 01Instruction Fields:SXO 000100 no RO - R7 1 0 n n nX1 000101 no NO - N7 o 1 1 n n nS dddddd S/L S ddddddYO 000110 no MO- M7 100nnnY1 000111 no SR 1 1 1 0 0 1AO 001000 no OMR 1 1 1 0 1 080 001001 no SP 1 1 1 0 1 1A2 001010 no SSH 11110082 001011 no SSL 1 1 1 1 0 1A1 001100 no LA 1 1 1 1 1 081 001101 no LC 1 1 1 1 1 1A 001110 yes (See Notes on page A-255)B 001111 yes (See Notes on page A-255)where "nnn" = Rn number (RO - R7)Nn number (NO - N7)Mn number (MO - M7)-
REP Repeat Next Instruction REPNotes: If A or B is specified as the destination operand, the following sequence of eventstakes place:1. The S bit is computed according to its definition (See Section A.5 CONDITION CODE COMPUTATION)2. The accumulator value is scaled according to the scaling mode bits SOand S1 in the status register (SR).3. If the accumulator extension is in use, the output of the shifter is limitedto the maximum positive or negative saturation constant, and the L bit isset.4. The LS 16 bits of the resulting 24 bit value is loaded into the loopcounter (LC). The original contents of A or B are not changed.If the system stack register SSH is specified as a source operand, the system stackpointer (SP) is postdecremented by 1 after SSH has been read.Timing: 4 oscillator clock cyclesMemory: 1 program word-
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
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3.1 DATA ARITHMETIC LOGIC UNITThis
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3.2.1 Data ALU Input Registers (X1,
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"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
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3.2.4 Accumulator ShifterThe accumu
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Table 3-1 Limited Data ValuesDestin
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_--- N BITS ---_TWOS COMPLEMENT INT
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CASE I: IF AO < $800000 (1/2), THEN
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one instruction cycle. The ANDI ins
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3.5 DATA ALU PROGRAMMING MODELThe D
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4.1 ADDRESS GENERATION UNIT AND ADD
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!---LOWADDRESS ALU -----I~.j.I.....
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•••••••• _ ........
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4.4.1 Address Register Indirect Mod
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EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
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EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
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EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
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Table 4-2 Address Modifier SummaryM
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ADDRESS -f-_POINTERUPPER BOUNDARYiM
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EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
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oundary gives a 16-bit binary numbe
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4.4.2.4 Address-Modifier-Type Encod
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SECTION 5PROGRAM CONTROL UNIT-
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X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
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interruptible since they are fetche
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PROGRAM CONTROL UNIT-23 1615 023 16
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The GGR is a special purpose contro
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If S 1 =0 and SO=O (no scaling)then
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-23 876543210I * 1* JSO I * I Mel y
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5.4.5.1 Stack Pointer (Bits 0-3)The
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-DATA ARITHMETIC LOGIC UNITINPUT RE
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6.1 INSTRUCTION SET INTRODUCTIONThe
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shown in Figure 6-2. Most instructi
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23 87 0L...-I ___-'-I_---'I BUS~ LS
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The MR and CCR may be accessed indi
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6.3.4 Operand ReferencesThe DSP sep
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Some address register indirect mode
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EXAMPLE A: IMMEDIATE INTO 24-BIT RE
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EXAMPLE A: IMMEDIATE SHORT INTO AO,
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EXAMPLE A: MOVE P: $3200,XOBEFORE E
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Table 6-1 Addressing Modes SummaryA
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6.4.2 LogicallnstructlonsThe logica
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START OF LOOP1)SP+ 1 • SP; LA. SS
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OPCODE/OPERANDSPARALLEL MOVE EXAMPL
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SECTION 7PROCESSING STATES-
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Each instruction requires a minimum
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second instruction of the downloade
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The DO instruction is another instr
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SP and SSH/SSL register manipulatio
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7.3.1 Interrupt TypesThe DSP56K rel
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Table 7-2 Status Register Interrupt
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7.3.3 Interrupt SourcesInterrupts c
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interrupts makes it very useful for
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MAINPROGRAMFETCHESLONG INTERRUPTSER
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7.3.3.3 Other Interrupt SourcesOthe
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7.3.4 Interrupt ArbitrationInterrup
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7.3.7 Interrupt Instruction Executi
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MAINPROGRAMMEMORYINTERRUPT SYNCHRON
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MAINPROGRAMFETCHESINTERRUPTSYNCHRON
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MAINPROGRAMFAST INTERRUPTVECTORLONG
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MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
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7.5 WAIT PROCESSING STATEThe WAIT i
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The stop processing state halts all
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the first instruction fetch). If th
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RESET -----------------------------
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16 - BIT INTERNALADDRESS BUSESX ADD
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8.2.2.1 Address (AO-A15)These three
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SECTION 9PLL CLOCK OSCILLATOR-
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X MEMORYRAM/ROMEXPANSION24-Bit56KMo
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23 22 21 20 19 18 17 16 15 14 13 12
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cleared. To enable rapid recovery w
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-CLVCCVCC for the CKOUT output. The
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4. For all input frequencies which
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While the PLL is regaining lock, th
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10.1 ON-CHIP EMULATION INTRODUCTION
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10.2.2 Debug Serial Clock/Chip Stat
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76543210I R/W I GO I EX I RS41 RS31
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shifted in (so a new command is ava
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10.3.4.4 Software Debug Occurrence
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10.4.4 Memory High Address Comparat
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10.6.1 External Debug Request Durin
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PABCIRCULARBUFFERPOINTERDSCKDSOFigu
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are serially available to the exter
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k. ACKI. ClKm. Send command READ FI
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19. ACK20. Send command READ GDB RE
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10.11.6.1 Case 1: Return To The Pre
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SECTION 11ADDITIONAL SUPPORTDr. BuB
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The following is a partial list of
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• In-line assembler language code
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I Document 10 I Version Synopsis I
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I Document ID I Version Synopsis I
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11.5 MOTOROLA DSP NEWSThe Motorola
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DIGITAL SIGNAL PROCESSINGAlan V. Op
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C Programming Language:Controls:. C
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Image Processing:DIGITAL IMAGE PROC
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LINEAR PREDICTION OF SPEECHJ. D. Ma
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A.1 APPENDIX A INTRODUCTIONThis app
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XnYnTable A-1 Instruction Descripti
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Table A-1 Instruction Description N
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Table A-1 Instruction Description N
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Table A-2 DSP56K Addressing ModesAd
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The address register indirect addre
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A.SCONDITION CODE COMPUTATION15 14
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S1 SO Scaling Mode Signed Integer P
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Table A-5 Condition Code Computatio
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A.7 INSTRUCTION DESCRIPTIONSThe fol
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ABSAbsolute ValueABSInstruction For
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ADC Add Long with Carry ADCresult.
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ADD Add ADDCondition Codes:15 14 13
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ADDL Shift Left and Add Accumulator
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ADDR Shift Right and Add Accumulato
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ANDLogical ANDANDInstruction Format
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ANDIAND Immediate with Control Regi
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ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGExplan
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and ChangeBCHGInstruct
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BCHG Bit Test and Change BCHGNotes:
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BCLR Bit Test and Clear BCLRExplana
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BClRBit Test and ClearBClRInstructi
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BClRBit Test and ClearBClRInstructi
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BClR Bit Test and Clear BClRNotes:
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BSET Bit Test and Set BSETExplanati
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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BSET Bit Test and Set BSETNotes: If
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BTSTBit TestBTSTCondition Codes:115
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8TSTBit Test8TSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLRClear AccumulatorCLRInstruction
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CMP Compare CMPCondition Codes:15 1
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CMPM Compare Magnitude CMPMConditio
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DEBUGEnter Debug ModeDEBUGOpcode:23
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DEBUGcc Enter Debug Mode Conditiona
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DEC Decrement by One DECInstruction
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DIV Divide Interation DIVThe DIV in
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DIV Divide Interation DIVNote that
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DIVInstruction Format:DIV S,DDivide
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DO Start Hardware Loop DOexecuted 6
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DOStart Hardware LoopDOAt LAOther R
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DOStart Hardware LoopDOInstruction
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DOStart Hardware LoopDOInstruction
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DO Start Hardware Loop DONotes: If
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ENDDO End Current DO Loop ENDDOExpl
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EOR Logical Exclusive OR EORInstruc
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ILLEGALIllegal Instruction Interrup
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INC Increment by One INCInstruction
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Jcc Jump Conditionally JccRestricti
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JccJump ConditionallyJccEffectiveAd
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JCLR Jump If Bit Clear JCLRRestrict
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JCLRJump If Bit ClearJCLRInstructio
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JCLR Jump If Bit Clear JCLRInstruct
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JMPJumpJMPInstruction Fields:xxx=12
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JSccJump to Subroutine Conditionall
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine If Bit Clea
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JSCLRJump to Subroutine If Bit Clea
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JSCLR Jump to Subroutine If Bit Cle
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JSET Jump if Bit Set JSETRestrictio
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JSETJump if Bit SetJSETInstruction
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JSET Jump If Bit Set JSETInstructio
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JSR Jump to Subroutine JSRInstructi
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JSSET Jump to Subroutine if Bit Set
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JSSETJump to Subroutine if Bit SetJ
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JSSET Jump to Subroutine if Bit Set
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LSL Logical Shift Left LSLCondition
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LSR Logical Shift Right LSRConditio
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LUALoad Updated AddressLUACondition
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MAC Signed Multiply-Accumulate MACC
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed MUltiply-Accumulate and
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MOVE Move Data MOVEExplanation of E
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MOVE Move Data MOVEWhen a 56-bit ac
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No Parallel Data MoveInstruction Fo
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I Immediate Short Data Move IExampl
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I Immediate Short Data Move IDDD d
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R Register to Register Data Move RE
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R Register to Register Data Move RI
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uAddress Register UpdateuInstructio
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X: X Memory Data Move X:Note:Due to
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X: X Memory Data Move X:S D DS,D d
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X: X Memory Data Move X:S D DS,D d
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X:R X Memory and Register Data Move
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Y: Y Memory Data Move Y:Note: This
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Y: Y Memory Data Move Y:S D DS,D d
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Y: Y Memory Data Move Y:S D DS,D d
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R:V Register and V Memory Data Move
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R:V Register and Y Memory Data Move
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R:V Register and Y Memory Data Move
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L: Long Memory Data Move L:Example:
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L: Long Memory Data Move L:Instruct
Page 443 and 444: X: Y: xv Memory Data Move X: Y:Exam
Page 445 and 446: X: Y: xv Memory Data Move X: Y:S1 D
Page 447 and 448: MOVEC Move Control Register MOVECst
Page 449 and 450: MOVEC Move Control Register MOVECCo
Page 451 and 452: MOVECMove Control RegisterMOVECInst
Page 453 and 454: MOVEC Move Control Register MOVECTi
Page 455 and 456: MOVEM Move Program Memory MOVEMoper
Page 457 and 458: MOVEM Move Program Memory MOVEMInst
Page 459 and 460: MOVEMMove Program MemoryMOVEMInstru
Page 461 and 462: MOVEP Move Peripheral Data MOVEPist
Page 463 and 464: MOVEP Move Peripheral Data MOVEPCon
Page 465 and 466: MOVEP Move Peripheral Data MOVEPIns
Page 467 and 468: MOVEP Move Peripheral Data MOVEPIns
Page 469 and 470: MPY Signed Multiply MPYExplanation
Page 471 and 472: MPY Signed Multiply MPYInstruction
Page 473 and 474: MPYR Signed Multiply and Round MPYR
Page 475 and 476: MPYR Signed Multiply and Round MPYR
Page 477 and 478: NEGNegate AccumulatorNEGInstruction
Page 479 and 480: NOPNo OperationNOPInstruction Forma
Page 481 and 482: NORM Normalize Accumulator Iteratio
Page 483 and 484: NOTLogical ComplementNOTInstruction
Page 485 and 486: ORLogical Inclusive ORORInstruction
Page 487 and 488: ORI OR Immediate with Control Regis
Page 489 and 490: REP Repeat Next Instruction REPRest
Page 491 and 492: REPRepeat Next InstructionREPInstru
Page 493: REPRepeat Next InstructionREPInstru
Page 497 and 498: RESETReset On-Chip Peripheral Devic
Page 499 and 500: RND Round Accumulator RNDConvergent
Page 501 and 502: RNDRound AccumulatorRNDInstruction
Page 503 and 504: ROL Rotate Left ROLCondition Codes:
Page 505 and 506: ROR Rotate Right RORCondition Codes
Page 507 and 508: RTIReturn from InterruptRTIConditio
Page 509 and 510: RTSReturn from SubroutineRTSInstruc
Page 511 and 512: sec Subtract Long with Carry secExp
Page 513 and 514: secSubtract Long with CarrysecInstr
Page 515 and 516: STOPStop Instruction ProcessingSTOP
Page 517 and 518: SUB Subtract SUBCondition Codes:S -
Page 519 and 520: SUBL Shift Left and Subtract Accumu
Page 521 and 522: SUBR Shift Right and Subtract Accum
Page 523 and 524: SWISoftware InterruptSWICondition C
Page 525 and 526: Tee Transfer Conditionally Teetion
Page 527 and 528: Tee Transfer Conditionally TeeInstr
Page 529 and 530: TFR Transfer Data ALU Register TFRC
Page 531 and 532: TSTTest AccumulatorTSTInstruction F
Page 533 and 534: WAIT Wait for Interrupt WAITConditi
Page 535 and 536: including the number of words per i
Page 537 and 538: 5. Compute final results.Thus, base
Page 539 and 540: JLC (R2+N2)will requireand will exe
Page 541 and 542: Table A-6 Instruction Timing Summar
Page 543 and 544: Note that the "ap" term in Table A-
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Table A-14 Memory Access Timing Sum
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Other RestrictionsDO SSH,xxxxJSR to
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Immediately before MOVEC from SSH o
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A.9.S REP RestrictionsThe REP instr
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Table A-18 Triple-Bit Register Enco
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Table A-24 Program Control Unit Reg
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R: Register to Register Parallel Da
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JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
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JSSET#n,S,xxxx23 16 15 87 000001011
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BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
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MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
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LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
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ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
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Table A-28 Operation Code QQQ Decod
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Table A-30 Special Case #10 P E R C
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NEGD23 87 43 0DATA BUS MOVE FIELDLS
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ADDRS,D23 87 43 oDATA BUS MOVE FIEL
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lEI
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Table 8-1 27-MHz Benchmark Results
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.*._---*-----*-------**-------....
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;Latest Revision - September 30, 19
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All coefficients are divided by 2:w
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Real input FFT based on Glenn Bergl
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countountcountcountorg y:coefset 0d
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; Real-Valued FFT for MOTOROLA DSP5
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; first group in the last passmove
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A Accumulator ....... ' ...........
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-H- fast ..........................
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PGND ..............................
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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