section 7 - Index of
section 7 - Index of section 7 - Index of
NOT Logical Complement NOTOperation:Assembler Syntax:0[47:24] -+ 0[47:24] (parallel move) NOT 0 (parallel move)where "-" denotes the logical NOT operatorDescription: Take the ones complement of bits 47-24 of the destination operand D andstore the result back in bits 47-24 of the destination accumulator. This is a 24-bit operation.The remaining bits of D are not affected.Example:NOT A 1 AB,L:(R2)+ ;save A 1 ,B 1 , take the ones complement of A 1Before ExecutionA~I ____ $0_0:_12_34_56_:7_89_A_BC __ ~AI~ __After Execution$_00_:E_DC_B_A9_:7_8_9A_B __ ~Explanation of Example: Prior to execution, the 56-bit A accumulator contains thevalue $OO:123456:789ABC. The NOT A instruction takes the ones complement of bits47-24 of the A accumulator (A1) and stores the result back in the A1 register. Theremaining bits of the A accumulator are not affected.Condition Codes:S -L -N -Z -V -15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I LF 1 OM 1 T 1** 181 180 1 11 1 10 lsi LIE 1 U N 1 z v 1 ~ I.~ MA ~_~ CCA _.Computed according to the definition in A.5 CONDITION CODE COMPUTATIONSet if data limiting has occurred during parallel moveSet if bit 47 of A or B result is setSet If bits 47-24 of A or B result are zeroAlways cleared
NOTLogical ComplementNOTInstruction Format:NOT 0Opcode:23DATA BUS MOVE FIELD 001OPTIONAL EFFECTIVE ADDRESS EXTENSION8 74 3 oo 1 I dInstruction Fields:o dA 08 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words
- Page 431 and 432: Y: Y Memory Data Move Y:S D DS,D d
- Page 433 and 434: R:V Register and V Memory Data Move
- Page 435 and 436: R:V Register and Y Memory Data Move
- Page 437 and 438: R:V Register and Y Memory Data Move
- Page 439 and 440: L: Long Memory Data Move L:Example:
- Page 441 and 442: L: Long Memory Data Move L:Instruct
- Page 443 and 444: X: Y: xv Memory Data Move X: Y:Exam
- Page 445 and 446: X: Y: xv Memory Data Move X: Y:S1 D
- Page 447 and 448: MOVEC Move Control Register MOVECst
- Page 449 and 450: MOVEC Move Control Register MOVECCo
- Page 451 and 452: MOVECMove Control RegisterMOVECInst
- Page 453 and 454: MOVEC Move Control Register MOVECTi
- Page 455 and 456: MOVEM Move Program Memory MOVEMoper
- Page 457 and 458: MOVEM Move Program Memory MOVEMInst
- Page 459 and 460: MOVEMMove Program MemoryMOVEMInstru
- Page 461 and 462: MOVEP Move Peripheral Data MOVEPist
- Page 463 and 464: MOVEP Move Peripheral Data MOVEPCon
- Page 465 and 466: MOVEP Move Peripheral Data MOVEPIns
- Page 467 and 468: MOVEP Move Peripheral Data MOVEPIns
- Page 469 and 470: MPY Signed Multiply MPYExplanation
- Page 471 and 472: MPY Signed Multiply MPYInstruction
- Page 473 and 474: MPYR Signed Multiply and Round MPYR
- Page 475 and 476: MPYR Signed Multiply and Round MPYR
- Page 477 and 478: NEGNegate AccumulatorNEGInstruction
- Page 479 and 480: NOPNo OperationNOPInstruction Forma
- Page 481: NORM Normalize Accumulator Iteratio
- Page 485 and 486: ORLogical Inclusive ORORInstruction
- Page 487 and 488: ORI OR Immediate with Control Regis
- Page 489 and 490: REP Repeat Next Instruction REPRest
- Page 491 and 492: REPRepeat Next InstructionREPInstru
- Page 493 and 494: REPRepeat Next InstructionREPInstru
- Page 495 and 496: REP Repeat Next Instruction REPNote
- Page 497 and 498: RESETReset On-Chip Peripheral Devic
- Page 499 and 500: RND Round Accumulator RNDConvergent
- Page 501 and 502: RNDRound AccumulatorRNDInstruction
- Page 503 and 504: ROL Rotate Left ROLCondition Codes:
- Page 505 and 506: ROR Rotate Right RORCondition Codes
- Page 507 and 508: RTIReturn from InterruptRTIConditio
- Page 509 and 510: RTSReturn from SubroutineRTSInstruc
- Page 511 and 512: sec Subtract Long with Carry secExp
- Page 513 and 514: secSubtract Long with CarrysecInstr
- Page 515 and 516: STOPStop Instruction ProcessingSTOP
- Page 517 and 518: SUB Subtract SUBCondition Codes:S -
- Page 519 and 520: SUBL Shift Left and Subtract Accumu
- Page 521 and 522: SUBR Shift Right and Subtract Accum
- Page 523 and 524: SWISoftware InterruptSWICondition C
- Page 525 and 526: Tee Transfer Conditionally Teetion
- Page 527 and 528: Tee Transfer Conditionally TeeInstr
- Page 529 and 530: TFR Transfer Data ALU Register TFRC
- Page 531 and 532: TSTTest AccumulatorTSTInstruction F
NOT Logical Complement NOTOperation:Assembler Syntax:0[47:24] -+ 0[47:24] (parallel move) NOT 0 (parallel move)where "-" denotes the logical NOT operatorDescription: Take the ones complement <strong>of</strong> bits 47-24 <strong>of</strong> the destination operand D andstore the result back in bits 47-24 <strong>of</strong> the destination accumulator. This is a 24-bit operation.The remaining bits <strong>of</strong> D are not affected.Example:NOT A 1 AB,L:(R2)+ ;save A 1 ,B 1 , take the ones complement <strong>of</strong> A 1Before ExecutionA~I ____ $0_0:_12_34_56_:7_89_A_BC __ ~AI~ __After Execution$_00_:E_DC_B_A9_:7_8_9A_B __ ~Explanation <strong>of</strong> Example: Prior to execution, the 56-bit A accumulator contains thevalue $OO:123456:789ABC. The NOT A instruction takes the ones complement <strong>of</strong> bits47-24 <strong>of</strong> the A accumulator (A1) and stores the result back in the A1 register. Theremaining bits <strong>of</strong> the A accumulator are not affected.Condition Codes:S -L -N -Z -V -15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I LF 1 OM 1 T 1** 181 180 1 11 1 10 lsi LIE 1 U N 1 z v 1 ~ I.~ MA ~_~ CCA _.Computed according to the definition in A.5 CONDITION CODE COMPUTATIONSet if data limiting has occurred during parallel moveSet if bit 47 <strong>of</strong> A or B result is setSet If bits 47-24 <strong>of</strong> A or B result are zeroAlways cleared