section 7 - Index of

section 7 - Index of section 7 - Index of

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MPY Signed Multiply MPYOperation:±S1 *S2 -+ D (parallel move)±S1 *S2 -+ D (parallel move)±(S1 *2-n)-+Q (no parallel move)Assembler Syntax:MPY (±)S1 ,S2,D (parallel move)MPY (±)S2,S1 ,D (parallel move)MPY (±)S,#n,D (no parallel move)Description: Multiply the two signed 24-bit source operands S1 and S2 and store theresulting product in the specified 56-bit destination accumulator D. Or, multiply thesigned 24-bit source operand S by the positive 24-bit immediate operand 2- n and add/subtract to/from the specified 56-bit destination accumulator D. The "_" sign option isused to negate the specified product prior to accumulation. The default sign option is "+".Note: When the processor is in the Double Precision Multiply Mode, the followinginstructions do not execute in the normal way and should only be used as part of thedouble precision multiply algorithm shown in Section 3.4 DOUBLE PRECISION MUL TI­PLY MODE:MPYYO, XO, AMACX1, YO, AMACXO, Y1, AMAC Y1, X1, AMPYYO, XO, BMACX1, YO, BMACXO, Y1, BMACY1, X1, BAll other Data ALU instructions are executed as NOP's when the processor is in the DoublePrecision Multiply Mode.Example 1:MPY -X1 ,Y1 ,A #$543210,YO;-(X1 *Y1) -+ A, update YOBefore ExecutionAfter ExecutionX1 I $800000 X1 I $800000Y1 I $COOOOO Y1 I $COOOOOAI $00:000000:000000 AI $FF:COOOOO:OOOOOO

MPY Signed Multiply MPYExplanation of Example 1: Prior to execution, the 24-bit X1 register contains the value$800000 (-1.0), the 24-bit Y1 register contains the value $COOOOO, (-0.5), and the 56-bitA accumulator contains the value $00:000000:000000 (0.0). The execution of the MPY­X1 ,Y1 ,A instruction multiples the 24-bit signed value in the X1 register by the 24-bitsigned value in the Y1 register, negates the 48-bit product, and stores the result in the56-bit A accumulator (-X1 *Y1 =-0.5=$FF:COOOOO:000000=A).Condition Codes:S -L -E -U -N -Z -V -15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I LF I DM I T I •• I 81 I 80 I 11 I 10 I 8 I LIE I u I N I z v I : I.~ MR •. ~ CCR _.Computed according to the definition in A.5 CONDITION CODE COMPUTATIONSet if limiting occurred during parallel moveSet if the signed integer portion of A or B result is in useSet if A or B result is unnormalizedSet if bit 55 of A or B result is setSet if A or B result equals zeroSet if overflow has occurred in A or B resultNot~: The definitions of the E and U bits vary according to the scaling mode being used.Refer to Section A.5 CONDITION CODE COMPUTATION for complete details.Instruction Format 1:MPY (±)S1,S2,0MPY (±)S2,S1,0Opcode 1:23DATA BUS MOVE FIELDOPTIONAL EFFECTIVE ADDRESS EXTENSION8 7 4 3I 1 Q Q Q I d koo

MPY Signed Multiply MPYExplanation <strong>of</strong> Example 1: Prior to execution, the 24-bit X1 register contains the value$800000 (-1.0), the 24-bit Y1 register contains the value $COOOOO, (-0.5), and the 56-bitA accumulator contains the value $00:000000:000000 (0.0). The execution <strong>of</strong> the MPY­X1 ,Y1 ,A instruction multiples the 24-bit signed value in the X1 register by the 24-bitsigned value in the Y1 register, negates the 48-bit product, and stores the result in the56-bit A accumulator (-X1 *Y1 =-0.5=$FF:COOOOO:000000=A).Condition Codes:S -L -E -U -N -Z -V -15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I LF I DM I T I •• I 81 I 80 I 11 I 10 I 8 I LIE I u I N I z v I : I.~ MR •. ~ CCR _.Computed according to the definition in A.5 CONDITION CODE COMPUTATIONSet if limiting occurred during parallel moveSet if the signed integer portion <strong>of</strong> A or B result is in useSet if A or B result is unnormalizedSet if bit 55 <strong>of</strong> A or B result is setSet if A or B result equals zeroSet if overflow has occurred in A or B resultNot~: The definitions <strong>of</strong> the E and U bits vary according to the scaling mode being used.Refer to Section A.5 CONDITION CODE COMPUTATION for complete details.Instruction Format 1:MPY (±)S1,S2,0MPY (±)S2,S1,0Opcode 1:23DATA BUS MOVE FIELDOPTIONAL EFFECTIVE ADDRESS EXTENSION8 7 4 3I 1 Q Q Q I d koo

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