section 7 - Index of
section 7 - Index of section 7 - Index of
L: Long Memory Data Move L:Instruction Format:( ..... ) L:ea,D( ..... ) S,L:eaOpcode:23 16 15 87001 OOLO L L/W 1 M M M R R R / INSTRUCTION OPCODEOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:ea=6-bit Effective Address=MMMRRRRegisterWEffectiveAddressing Mode M M M R R RReadS 0 (Rn)-Nn 0 0 0 r r rWrite D 1 (Rn)+Nn 0 0 1 r r r(Rn)- 0 1 0 r(Rn)+ 0 1 1 r(Rn) 1 0 0 r r(Rn+Nn) 1 0 1 r r r-(Rn) 1 1 0 r r rAbsolute address 1 1 0 0 0 0where "rrr" refers to an address register RO-R75 D DS 51 52 S/L D D1 D2 Sign Ext Zero L L LA10 A1 AO no A10 A1 AO no noB10 B1 BO no B10 B1 BO no no 0 0o 0 1X X1 XO no X X1 XO no no 010Y Y1 YO no Y Y1 YO no no o 1 1A A1 AO yes A A1 AO A2 no 1 0 0B B1 BO yes B B1 BO B2 no 1 0 1AB A B yes AB A B A2,B2 AO,BO 1 1 0BA B A yes BA B A B2,A2 BO,AO 1 1 1Timing: mv oscillator clock cyclesMemory: mv program words
L: Long Memory Data Move L:Instruction Format:( ..... ) L:aa,D( ..... ) S,L:aaOpcode:23 16 15 8 7 0o 1 0 0 L 0 L L I W 0 a a a a a a INSTRUCTION OPCODEInstruction Fields:aa=6-bit Absolute Short Address=aaaaaaRegister WAbsolute Short Address aaaaaaReadS 0 000000Write D 1 ••111111S D DS S1 82 S/L D 01 02 Sign Ext Zero L L LA10 A1 AO no A10 A1 AO no no 000B10 B1 BO no B10 B1 BO no no o 0 1X X1 XO no X X1 XO no no 010Y Y1 YO no Y Y1 YO no no 011A A1 AO yes A A1 AO A2 no 1 0 0B B1 BO yes B B1 BO B2 no 1 0 1AB A B yes AB A B A2,B2 AO,BO 1 1 0BA B A yes BA B A B2,A2 BO,AO 1 1 1Timing: mv oscillator clock cyclesMemory: mv program words-
- Page 389 and 390: LUALoad Updated AddressLUACondition
- Page 391 and 392: MAC Signed Multiply-Accumulate MACC
- Page 393 and 394: MACSigned Multiply-AccumulateMACTim
- Page 395 and 396: MACR Signed Multiply-Accumulate and
- Page 397 and 398: MACR Signed MUltiply-Accumulate and
- Page 399 and 400: MOVE Move Data MOVEExplanation of E
- Page 401 and 402: MOVE Move Data MOVEWhen a 56-bit ac
- Page 403 and 404: No Parallel Data MoveInstruction Fo
- Page 405 and 406: I Immediate Short Data Move IExampl
- Page 407 and 408: I Immediate Short Data Move IDDD d
- Page 409 and 410: R Register to Register Data Move RE
- Page 411 and 412: R Register to Register Data Move RI
- Page 413 and 414: uAddress Register UpdateuInstructio
- Page 415 and 416: X: X Memory Data Move X:Note:Due to
- Page 417 and 418: X: X Memory Data Move X:S D DS,D d
- Page 419 and 420: X: X Memory Data Move X:S D DS,D d
- Page 421 and 422: X:R X Memory and Register Data Move
- Page 423 and 424: X:R X Memory and Register Data Move
- Page 425 and 426: X:R X Memory and Register Data Move
- Page 427 and 428: Y: Y Memory Data Move Y:Note: This
- Page 429 and 430: Y: Y Memory Data Move Y:S D DS,D d
- Page 431 and 432: Y: Y Memory Data Move Y:S D DS,D d
- Page 433 and 434: R:V Register and V Memory Data Move
- Page 435 and 436: R:V Register and Y Memory Data Move
- Page 437 and 438: R:V Register and Y Memory Data Move
- Page 439: L: Long Memory Data Move L:Example:
- Page 443 and 444: X: Y: xv Memory Data Move X: Y:Exam
- Page 445 and 446: X: Y: xv Memory Data Move X: Y:S1 D
- Page 447 and 448: MOVEC Move Control Register MOVECst
- Page 449 and 450: MOVEC Move Control Register MOVECCo
- Page 451 and 452: MOVECMove Control RegisterMOVECInst
- Page 453 and 454: MOVEC Move Control Register MOVECTi
- Page 455 and 456: MOVEM Move Program Memory MOVEMoper
- Page 457 and 458: MOVEM Move Program Memory MOVEMInst
- Page 459 and 460: MOVEMMove Program MemoryMOVEMInstru
- Page 461 and 462: MOVEP Move Peripheral Data MOVEPist
- Page 463 and 464: MOVEP Move Peripheral Data MOVEPCon
- Page 465 and 466: MOVEP Move Peripheral Data MOVEPIns
- Page 467 and 468: MOVEP Move Peripheral Data MOVEPIns
- Page 469 and 470: MPY Signed Multiply MPYExplanation
- Page 471 and 472: MPY Signed Multiply MPYInstruction
- Page 473 and 474: MPYR Signed Multiply and Round MPYR
- Page 475 and 476: MPYR Signed Multiply and Round MPYR
- Page 477 and 478: NEGNegate AccumulatorNEGInstruction
- Page 479 and 480: NOPNo OperationNOPInstruction Forma
- Page 481 and 482: NORM Normalize Accumulator Iteratio
- Page 483 and 484: NOTLogical ComplementNOTInstruction
- Page 485 and 486: ORLogical Inclusive ORORInstruction
- Page 487 and 488: ORI OR Immediate with Control Regis
- Page 489 and 490: REP Repeat Next Instruction REPRest
L: Long Memory Data Move L:Instruction Format:( ..... ) L:ea,D( ..... ) S,L:eaOpcode:23 16 15 87001 OOLO L L/W 1 M M M R R R / INSTRUCTION OPCODEOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:ea=6-bit Effective Address=MMMRRRRegisterWEffectiveAddressing Mode M M M R R RReadS 0 (Rn)-Nn 0 0 0 r r rWrite D 1 (Rn)+Nn 0 0 1 r r r(Rn)- 0 1 0 r(Rn)+ 0 1 1 r(Rn) 1 0 0 r r(Rn+Nn) 1 0 1 r r r-(Rn) 1 1 0 r r rAbsolute address 1 1 0 0 0 0where "rrr" refers to an address register RO-R75 D DS 51 52 S/L D D1 D2 Sign Ext Zero L L LA10 A1 AO no A10 A1 AO no noB10 B1 BO no B10 B1 BO no no 0 0o 0 1X X1 XO no X X1 XO no no 010Y Y1 YO no Y Y1 YO no no o 1 1A A1 AO yes A A1 AO A2 no 1 0 0B B1 BO yes B B1 BO B2 no 1 0 1AB A B yes AB A B A2,B2 AO,BO 1 1 0BA B A yes BA B A B2,A2 BO,AO 1 1 1Timing: mv oscillator clock cyclesMemory: mv program words
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