section 7 - Index of
section 7 - Index of section 7 - Index of
R:VRegister and V Memory Oata MoveR:VInstruction Fields:ea=6-bit Effective Address=MMMRRREffectiveRegisterW Addressing Mode MRead S2 0 (Rn)-Nn 0Write D2 1 (Rn)+Nn 0(Rn)- 0. (Rn)+ 0(Rn) 1(Rn+Nn) 1-(Rn) 1Absolute address 1Immediate data 1where "rrr" refers to an address register RO-R7M M R R R0 0 r r r0 1 r r r1 0 r r1 1 r r0 0 r r0 1 r r r1 1 r r r1 0 0 01 0 1 o 051 0151 d S/L 01 e 5ign Ext01Zero52,02 f f52 02 025/L Sign Ext ZeroA 0 yes XO 0 noB 1 yes X1 nononoYO o 0Y1 o 1A 1 0B 1 1no no nono no noyes A2 AOyes B2 BOTiming: mv oscillator clock cyclesMemory: mv program words
R:V Register and Y Memory Data Move R:VClass II Instruction Format:( ..... ) YO ~ A A ~ Y:ea( ..... ) YO ~ 8 8 ~ Y:eaOpcode:23 16 15 8 7 000001 0 0 d 110M M M R R R 1 INSTRUCTION OPCODEOPTIONAL EFFECTIVE ADDRESS EXTENSION·Instructlon Fields:ea=6-bit Effective Address=MMMRRREffectiveAddressing ModeMMMRRRo 0 o r r r(Rn)-Nn(Rn)+Nn0 1 r r r(Rn)-1 0 r r(Rn)+o 1 1 r r(Rn)1 0 o r r r(Rn+Nn) 1 0 1 r r-(Rn) 1 1 1 r rwhere "rrr" refers to an address register RO-R7S,DXOYOA8SRCS/LnonoyesyesDESTSign ExtN/AN/AA282DESTZeroN/AN/AAO80do1MOVEOpcodeYO ~ A A.~ Y:eaYO ~ 8 8~Y:eaTiming: mv oscillator clock cyclesMemory: mv program words
- Page 385 and 386: LSL Logical Shift Left LSLCondition
- Page 387 and 388: LSR Logical Shift Right LSRConditio
- Page 389 and 390: LUALoad Updated AddressLUACondition
- Page 391 and 392: MAC Signed Multiply-Accumulate MACC
- Page 393 and 394: MACSigned Multiply-AccumulateMACTim
- Page 395 and 396: MACR Signed Multiply-Accumulate and
- Page 397 and 398: MACR Signed MUltiply-Accumulate and
- Page 399 and 400: MOVE Move Data MOVEExplanation of E
- Page 401 and 402: MOVE Move Data MOVEWhen a 56-bit ac
- Page 403 and 404: No Parallel Data MoveInstruction Fo
- Page 405 and 406: I Immediate Short Data Move IExampl
- Page 407 and 408: I Immediate Short Data Move IDDD d
- Page 409 and 410: R Register to Register Data Move RE
- Page 411 and 412: R Register to Register Data Move RI
- Page 413 and 414: uAddress Register UpdateuInstructio
- Page 415 and 416: X: X Memory Data Move X:Note:Due to
- Page 417 and 418: X: X Memory Data Move X:S D DS,D d
- Page 419 and 420: X: X Memory Data Move X:S D DS,D d
- Page 421 and 422: X:R X Memory and Register Data Move
- Page 423 and 424: X:R X Memory and Register Data Move
- Page 425 and 426: X:R X Memory and Register Data Move
- Page 427 and 428: Y: Y Memory Data Move Y:Note: This
- Page 429 and 430: Y: Y Memory Data Move Y:S D DS,D d
- Page 431 and 432: Y: Y Memory Data Move Y:S D DS,D d
- Page 433 and 434: R:V Register and V Memory Data Move
- Page 435: R:V Register and Y Memory Data Move
- Page 439 and 440: L: Long Memory Data Move L:Example:
- Page 441 and 442: L: Long Memory Data Move L:Instruct
- Page 443 and 444: X: Y: xv Memory Data Move X: Y:Exam
- Page 445 and 446: X: Y: xv Memory Data Move X: Y:S1 D
- Page 447 and 448: MOVEC Move Control Register MOVECst
- Page 449 and 450: MOVEC Move Control Register MOVECCo
- Page 451 and 452: MOVECMove Control RegisterMOVECInst
- Page 453 and 454: MOVEC Move Control Register MOVECTi
- Page 455 and 456: MOVEM Move Program Memory MOVEMoper
- Page 457 and 458: MOVEM Move Program Memory MOVEMInst
- Page 459 and 460: MOVEMMove Program MemoryMOVEMInstru
- Page 461 and 462: MOVEP Move Peripheral Data MOVEPist
- Page 463 and 464: MOVEP Move Peripheral Data MOVEPCon
- Page 465 and 466: MOVEP Move Peripheral Data MOVEPIns
- Page 467 and 468: MOVEP Move Peripheral Data MOVEPIns
- Page 469 and 470: MPY Signed Multiply MPYExplanation
- Page 471 and 472: MPY Signed Multiply MPYInstruction
- Page 473 and 474: MPYR Signed Multiply and Round MPYR
- Page 475 and 476: MPYR Signed Multiply and Round MPYR
- Page 477 and 478: NEGNegate AccumulatorNEGInstruction
- Page 479 and 480: NOPNo OperationNOPInstruction Forma
- Page 481 and 482: NORM Normalize Accumulator Iteratio
- Page 483 and 484: NOTLogical ComplementNOTInstruction
- Page 485 and 486: ORLogical Inclusive ORORInstruction
R:V Register and Y Memory Data Move R:VClass II Instruction Format:( ..... ) YO ~ A A ~ Y:ea( ..... ) YO ~ 8 8 ~ Y:eaOpcode:23 16 15 8 7 000001 0 0 d 110M M M R R R 1 INSTRUCTION OPCODEOPTIONAL EFFECTIVE ADDRESS EXTENSION·Instructlon Fields:ea=6-bit Effective Address=MMMRRREffectiveAddressing ModeMMMRRRo 0 o r r r(Rn)-Nn(Rn)+Nn0 1 r r r(Rn)-1 0 r r(Rn)+o 1 1 r r(Rn)1 0 o r r r(Rn+Nn) 1 0 1 r r-(Rn) 1 1 1 r rwhere "rrr" refers to an address register RO-R7S,DXOYOA8SRCS/LnonoyesyesDESTSign ExtN/AN/AA282DESTZeroN/AN/AAO80do1MOVEOpcodeYO ~ A A.~ Y:eaYO ~ 8 8~Y:eaTiming: mv oscillator clock cyclesMemory: mv program words
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