section 7 - Index of
section 7 - Index of section 7 - Index of
R:Y Register and Y Memory Data Move R:YClass II Example:MAC XO,YO,A YO,B B,Y:(R1)+Before ExecutionXO I $400000;multiply XO and YO and accumulate in A;move B to Y memory location pointed to;by R1 and postincrement R1;move YO to BAfter Executionxo I $400000YO I $600000YO I $600000AI$00:000000:000000AI$00:300000:000000BI$00:800000:000000BI$00:600000:000000Y:$1234 I $000000Y:$1234 I$7FFFFFR1I$1234R1 I $1235Explanation of the Class II Example: Prior to execution, the 24-bit registers, XO andYO, contain $400000 and $600000, respectively. The 56-bit accumulators A and B containthe values $00:000000:000000 and $00:800000:000000 (+1.0000), respectively.The 24-bit Y memory location Y:$1234 contains the value $000000, and the 16-bit R1register contains the value $1234. Execution of the parallel move portion of the instruction(yO,B B,Y:(R1)+) moves the YO register ($600000) into accumulator B1 ($600000),sign extends B1 into B2 ($00), and zero fills BO ($000000). It also moves the 24-bit limitedvalue of B ($7FFFFF) into the Y:$1234 memory location and increments R1 to$1235.
R:V Register and Y Memory Data Move R:YCondition Codes:115 14 13 12 11 10 9 8 7 6 5 4 3 2 0LF 1 OM 1 T 1** 1 SI 1 SO 1 11 I lois 1 I I I L E U N z I v CCR 1 :1~ MR ....S -L -Computed according to the definition in A.5 CONDITION CODE COMPUTATIONSet if data limiting has occurred during parallel move.Class I Instruction Format:( ..... ) S1 ,D1 Y:ea,D2( ..... ) S1 ,D1 S2,Y:ea( ..... ) S1 ,D1 #xxxxxx,D2Opcode:23 16 15 8 7 00001def f Iw 1 M M M R R R I INSTRUCTION OPCODEOPTIONAL EFFECTIVE ADDRESS EXTENSION
- Page 383 and 384: JSSET Jump to Subroutine if Bit Set
- Page 385 and 386: LSL Logical Shift Left LSLCondition
- Page 387 and 388: LSR Logical Shift Right LSRConditio
- Page 389 and 390: LUALoad Updated AddressLUACondition
- Page 391 and 392: MAC Signed Multiply-Accumulate MACC
- Page 393 and 394: MACSigned Multiply-AccumulateMACTim
- Page 395 and 396: MACR Signed Multiply-Accumulate and
- Page 397 and 398: MACR Signed MUltiply-Accumulate and
- Page 399 and 400: MOVE Move Data MOVEExplanation of E
- Page 401 and 402: MOVE Move Data MOVEWhen a 56-bit ac
- Page 403 and 404: No Parallel Data MoveInstruction Fo
- Page 405 and 406: I Immediate Short Data Move IExampl
- Page 407 and 408: I Immediate Short Data Move IDDD d
- Page 409 and 410: R Register to Register Data Move RE
- Page 411 and 412: R Register to Register Data Move RI
- Page 413 and 414: uAddress Register UpdateuInstructio
- Page 415 and 416: X: X Memory Data Move X:Note:Due to
- Page 417 and 418: X: X Memory Data Move X:S D DS,D d
- Page 419 and 420: X: X Memory Data Move X:S D DS,D d
- Page 421 and 422: X:R X Memory and Register Data Move
- Page 423 and 424: X:R X Memory and Register Data Move
- Page 425 and 426: X:R X Memory and Register Data Move
- Page 427 and 428: Y: Y Memory Data Move Y:Note: This
- Page 429 and 430: Y: Y Memory Data Move Y:S D DS,D d
- Page 431 and 432: Y: Y Memory Data Move Y:S D DS,D d
- Page 433: R:V Register and V Memory Data Move
- Page 437 and 438: R:V Register and Y Memory Data Move
- Page 439 and 440: L: Long Memory Data Move L:Example:
- Page 441 and 442: L: Long Memory Data Move L:Instruct
- Page 443 and 444: X: Y: xv Memory Data Move X: Y:Exam
- Page 445 and 446: X: Y: xv Memory Data Move X: Y:S1 D
- Page 447 and 448: MOVEC Move Control Register MOVECst
- Page 449 and 450: MOVEC Move Control Register MOVECCo
- Page 451 and 452: MOVECMove Control RegisterMOVECInst
- Page 453 and 454: MOVEC Move Control Register MOVECTi
- Page 455 and 456: MOVEM Move Program Memory MOVEMoper
- Page 457 and 458: MOVEM Move Program Memory MOVEMInst
- Page 459 and 460: MOVEMMove Program MemoryMOVEMInstru
- Page 461 and 462: MOVEP Move Peripheral Data MOVEPist
- Page 463 and 464: MOVEP Move Peripheral Data MOVEPCon
- Page 465 and 466: MOVEP Move Peripheral Data MOVEPIns
- Page 467 and 468: MOVEP Move Peripheral Data MOVEPIns
- Page 469 and 470: MPY Signed Multiply MPYExplanation
- Page 471 and 472: MPY Signed Multiply MPYInstruction
- Page 473 and 474: MPYR Signed Multiply and Round MPYR
- Page 475 and 476: MPYR Signed Multiply and Round MPYR
- Page 477 and 478: NEGNegate AccumulatorNEGInstruction
- Page 479 and 480: NOPNo OperationNOPInstruction Forma
- Page 481 and 482: NORM Normalize Accumulator Iteratio
- Page 483 and 484: NOTLogical ComplementNOTInstruction
R:V Register and Y Memory Data Move R:YCondition Codes:115 14 13 12 11 10 9 8 7 6 5 4 3 2 0LF 1 OM 1 T 1** 1 SI 1 SO 1 11 I lois 1 I I I L E U N z I v CCR 1 :1~ MR ....S -L -Computed according to the definition in A.5 CONDITION CODE COMPUTATIONSet if data limiting has occurred during parallel move.Class I Instruction Format:( ..... ) S1 ,D1 Y:ea,D2( ..... ) S1 ,D1 S2,Y:ea( ..... ) S1 ,D1 #xxxxxx,D2Opcode:23 16 15 8 7 00001def f Iw 1 M M M R R R I INSTRUCTION OPCODEOPTIONAL EFFECTIVE ADDRESS EXTENSION
Change language