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R:V Register and V Memory Data Move R:VOperation:Assembler Syntax:Class IClass I( ..... ); S1--+01 ; Y:ea--+02 ( ..... ) S1 ,01 Y:ea,02( ..... ); S1--+01; S2--+Y:ea ( ..... ) S1 ,01 S2,Y:ea( ..... ); S1--+01 ; #xxxxxx--+02 ( ..... ) S1 ,01 #xxxxxx,02Class IIClass II( ..... ); YO --+A; A--+Y:ea ( ..... ) YO,A A,Y:ea( ..... ); YO--+B; B--+Y:ea ( ..... ) YO,B B,Y:eawhere ( ..... ) refers to any arithmetic or logical instruction which allows parallel moves.Description: Class I: Move a one-word operand from an accumulator (S1) to an inputregister (01) and move another word operand from/to Y memory. All memory addressingmodes, including absolute addressing and 24-bit immediate data, may be used. The registerto register move (S1 ,01) allows a data ALU accumulator to be moved to a data ALUinput register for use as a data ALU operand in the following instruction.Class II: Move one-word operand from a data ALU accumulator to Y memory and onewordoperand from data ALU register YO to a data ALU accumulator. One effectiveaddress is specified. All memory addressing modes, excluding long absolute addressingand long immediate data, may be used. Class II move operations have been added tothe R:Y parallel move (and a similar feature has been added to the X:R parallel move) asan added feature available in the first quarter <strong>of</strong> 1989.For both Class I and Class II R:Y parallel data moves, if the arithmetic or logical opcodeoperandportion <strong>of</strong> the instruction specifies a given destination accumulator, that sameaccumulator or portion <strong>of</strong> that accumulator may not be specified as a destination 02 inthe parallel data bus move operation. Thus, if the opcode-operand portion <strong>of</strong> the instructionspecifies the 56-bit A accumulator as its destination, the parallel data bus move portion<strong>of</strong> the instruction may not specify AO, A1, A2, or A as its destination 02. Similarly, ifthe opcode-operand portion <strong>of</strong> the instruction specifies the 56-bit B accumulator as itsdestination, the parallel data bus move portion <strong>of</strong> the ins~ruction may not specify BO, B1,B2, or B as its destination 02. That is, duplicate destinations are NOT allowed within thesame instruction.

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