section 7 - Index of

X:R X Memory and Register Data Move X:RCondition Codes:I15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0LF I DM I T I ** I S1 I SO I 11 I 10 I SAlII( MR••CCRI L I E I U N I z vI ~IS -L -Computed according to the definition in A.S CONDITION CODE COMPUTATIONSet if data limiting has occurred during parallel move.Class I Instruction Format:( ..... ) X:ea,D1 S2,D2( ..... ) S1 ,X:ea S2, D2( ..... ) #Xxxxxx, S2,D2Opcode:23 16 15 870o 0 0 1 f f d f Jw 0 M M M R R R l INSTRUCTION OPCODEInstruction Fields:ea=6-bit Effective Address=MMMRRROPTIONAL EFFECTIVE ADDRESS EXTENSIONEffectiveRegisterW Addressing Mode M M M R R RReadS 0 (Rn)-Nn 0 0 0 r rWrite 0 1 (Rn)+Nn 0 0 1 r r(Rn)- 0 1 o r r r(Rn)+ 0 1 1(Rn) 1 0 0(Rn+Nn) 1 0 1 r r r-(Rn) 1 1 1 r r rAbsolute address 1 1 0 0 0 0Immediate data 1 1 0 1 0 0where "rrr" refers to an address register RO-R7