section 7 - Index of

section 7 - Index of section 7 - Index of

11.07.2015 Views

X: X Memory Data Move X:Operation:Assem bier Syntax:( ..... ); X:ea~D ( ..... ) X:ea,D( ..... ); X:aa~D ( ..... ) X:aa,D( ..... ); S~X:ea ( ..... ) S,X:ea( ..... ); S~X:aa ( ..... ) S,X:aa( ..... );#xxxxxx~D ( ..... ) #xxxxxx,Dwhere ( ..... ) refers to any arithmetic or logical instruction which allows parallel moves.Description: Move the specified word operand from/to X memory. All memory addressingmodes, including absolute addressing and 24-bit immediate data, may be used.Absolute short addressing may also be used.If the arithmetic or logical opcode-operand portion of the instruction specifies a givendestination accumulator, that same accumulator or portion of that accumulator may notbe specified as a destination D in the parallel data bus move operation. Thus, if theopcode-operand portion of the instruction specifies the 56-bit A accumu lator as its destination,the parallel data bus move portion of the instruction may not specify AO, A 1, A2,or A as its destination D. Similarly, if the opcode-operand portion of the instruction specifiesthe 56-bit 8 accumulator as its destination, the parallel data bus move portion of theinstruction may not specify 80, 81, 82, or B as its destination D. That is, duplicate destinationsare NOT allowed within the same instruction.If the opcode-operand portion of the instruction specifies a given source or destinationregister, that same register or portion of that register may be used as a source S in theparallel data bus move operation. This allows data to be moved in the same instruction inwhich it is being used as a source operand by a data ALU operation. That is, duplicatesources are allowed within the same instruction.When a 24-bit source operand is moved into a 16-bit destination register, the 16 LS bitsof the 24-bit source operand are stored in the 16-bit destination register. When a 16-bitsource operand is moved into a 24-bit destination register, the 16 LS bits of the destinationregister are loaded with the contents of the 16-bit source operand, and the eight MSbits of the 24-bit destination register are zeroed.

X: X Memory Data Move X:Note:Due to instruction pipelining, if an AGU register (Mn, Nn, or Rn) is directly changedwith this instruction, the new contents may not be available for use until the second followinginstruction. See the restrictions discussed in A.9.6 - R, N, and M Register R~strictionson page A-31 o.Example:ASL A R2,X:-(R2) ;A*2-+A, save updated R2 in X:(R2)~1~ ______Before ExecutionX:$1000 1~ _____ $0_0_00_00 ______ ~After Execution$_10_01 ______ ~ R2~1 ______ ~$1_00_0 ____ ~X:$1000 ~I ______ $0_01_00_0 ____ ~Explanation of Example: Prior to execution, the 16-bit R2 address register contains thevalue $1001, and the 24-bit X memory location X:$1000 contains the value $000000.The execution of the parallel move portion of the instruction, R2,X:-(R2), predecrementsthe R2 address register and then uses the R2 address register to move the updated contentsof the R2 address register into the 24-bit X memory location X:$1 000.Condition Codes:S -L -Computed according to the definition in A.5 CONDITION CODE COMPUTATION.Set if data limiting has occurred during parallel move.Note: The MOVE A,X:ea operation will result in a 24-bit positive or negative saturationconstant being stored in the specified 24-bit X memory location if the signed integer portionof the A accumulator is in use.

X: X Memory Data Move X:Note:Due to instruction pipelining, if an AGU register (Mn, Nn, or Rn) is directly changedwith this instruction, the new contents may not be available for use until the second followinginstruction. See the restrictions discussed in A.9.6 - R, N, and M Register R~strictionson page A-31 o.Example:ASL A R2,X:-(R2) ;A*2-+A, save updated R2 in X:(R2)~1~ ______Before ExecutionX:$1000 1~ _____ $0_0_00_00 ______ ~After Execution$_10_01 ______ ~ R2~1 ______ ~$1_00_0 ____ ~X:$1000 ~I ______ $0_01_00_0 ____ ~Explanation <strong>of</strong> Example: Prior to execution, the 16-bit R2 address register contains thevalue $1001, and the 24-bit X memory location X:$1000 contains the value $000000.The execution <strong>of</strong> the parallel move portion <strong>of</strong> the instruction, R2,X:-(R2), predecrementsthe R2 address register and then uses the R2 address register to move the updated contents<strong>of</strong> the R2 address register into the 24-bit X memory location X:$1 000.Condition Codes:S -L -Computed according to the definition in A.5 CONDITION CODE COMPUTATION.Set if data limiting has occurred during parallel move.Note: The MOVE A,X:ea operation will result in a 24-bit positive or negative saturationconstant being stored in the specified 24-bit X memory location if the signed integer portion<strong>of</strong> the A accumulator is in use.

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