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section 7 - Index of

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RRegister to Register Data MoveROperation:( ..... ); S-+DAssembler Syntax:( ..... ) S,Dwhere ( ..... ) refers to any arithmetic or logical instruction which allows parallel moves.Description: Move the source register S to the destination register D.If the arithmetic or logical opcode-operand portion <strong>of</strong> the instruction specifies a givendestination accumulator, that same accumulator or portion <strong>of</strong> that accumulator may notbe specified as a destination D in the parallel data bus move operation. Thus, if theopcode-operand portion <strong>of</strong> the instruction specifies the 56-bit A accumulator as its destination,the parallel data bus move portion <strong>of</strong> the instruction may not specify AO, A 1, A2,or A as its destination D. Similarly, if the opcode-operand portion <strong>of</strong> the instruction specifiesthe 56-bit B accumulator as its destination, the parallel data bus move portion <strong>of</strong> theinstruction may not specify BO, B1, B2, or B as its destination D. That is, duplicate destinationsare NOT allowed within the same Instruction.If the opcode-operand portion <strong>of</strong> the instruction specifies a given source or destinationregister, that same register or portion <strong>of</strong> that register may be used as a source S in theparallel data bus move operation. This allows data to be moved in the same instruction inwhich it is being used as a source operand by a data ALU operation. That is,duplicatesources are allowed within the same instruction.When a 24-bit source operand is moved into a 16-bit destination register, the 16 LS bits<strong>of</strong> the 24-bit source operand are stored in the 16-bit destination register. When a 16-bitsource operand is moved into a 24-bit destination register, the 16 LS bits <strong>of</strong> the destinationregister are loaded with the contents <strong>of</strong> the 16-bit source operand, and the eight MSbits <strong>of</strong> the 24-bit destination register are zeroed.-Note: The MOVE A,B operation will result in a 24-bit positive or negative saturation constantbeing stored in the B1 portion <strong>of</strong> the B accumulator if the signed integer portion <strong>of</strong>the A accumulator is in use.Note: Due to instruction pipelining, if an AGU register (Mn, Nn, or Rn) is directly changedwith this instruction, the new contents may not be available for use until the second followinginstruction. See the restrictions discussed in A.9.6 - R, N, and M Register Restrictionson page A-310.

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