section 7 - Index of
section 7 - Index of section 7 - Index of
No Parallel Data MoveOperation:Assembler Syntax:( ..... ) ( ..... )where ( ..... ) refers to any arithmetic or logical instruction which allows parallel moves.Description: Many (30 of the total 66) instructions in the DSP56K instruction set allowparallel moves. The parallel moves have been divided into 10 opcode categories. Thiscategory is a parallel move NOP and does not involve data bus move activity.Example:ADD XO,A;add XO to A (no parallel move)Explanation of Example: This is an example of an instruction which allows parallelmoves but does not have one.Condition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 oI LF I DM I T I - I S1 I SO I 11 I 10 I S I L I E I u N I z~ MR .. III( CCRThe condition codes are affected by the instruction, not the move.-
No Parallel Data MoveInstruction Format:( ..... )Opcode:23 15 80010000000000000INSTRUCTION OPCODEoInstruction Format:(defined by instruction)Timing: mv oscillator clock cyclesMemory: mv program words-
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
- Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
- Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
- Page 359 and 360: JSccJump to Subroutine Conditionall
- Page 361 and 362: JScc Jump to Subroutine Conditional
- Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
- Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
- Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
- Page 369 and 370: JSCLR Jump to Subroutine If Bit Cle
- Page 371 and 372: JSET Jump if Bit Set JSETRestrictio
- Page 373 and 374: JSETJump if Bit SetJSETInstruction
- Page 375 and 376: JSET Jump If Bit Set JSETInstructio
- Page 377 and 378: JSR Jump to Subroutine JSRInstructi
- Page 379 and 380: JSSET Jump to Subroutine if Bit Set
- Page 381 and 382: JSSETJump to Subroutine if Bit SetJ
- Page 383 and 384: JSSET Jump to Subroutine if Bit Set
- Page 385 and 386: LSL Logical Shift Left LSLCondition
- Page 387 and 388: LSR Logical Shift Right LSRConditio
- Page 389 and 390: LUALoad Updated AddressLUACondition
- Page 391 and 392: MAC Signed Multiply-Accumulate MACC
- Page 393 and 394: MACSigned Multiply-AccumulateMACTim
- Page 395 and 396: MACR Signed Multiply-Accumulate and
- Page 397 and 398: MACR Signed MUltiply-Accumulate and
- Page 399 and 400: MOVE Move Data MOVEExplanation of E
- Page 401: MOVE Move Data MOVEWhen a 56-bit ac
- Page 405 and 406: I Immediate Short Data Move IExampl
- Page 407 and 408: I Immediate Short Data Move IDDD d
- Page 409 and 410: R Register to Register Data Move RE
- Page 411 and 412: R Register to Register Data Move RI
- Page 413 and 414: uAddress Register UpdateuInstructio
- Page 415 and 416: X: X Memory Data Move X:Note:Due to
- Page 417 and 418: X: X Memory Data Move X:S D DS,D d
- Page 419 and 420: X: X Memory Data Move X:S D DS,D d
- Page 421 and 422: X:R X Memory and Register Data Move
- Page 423 and 424: X:R X Memory and Register Data Move
- Page 425 and 426: X:R X Memory and Register Data Move
- Page 427 and 428: Y: Y Memory Data Move Y:Note: This
- Page 429 and 430: Y: Y Memory Data Move Y:S D DS,D d
- Page 431 and 432: Y: Y Memory Data Move Y:S D DS,D d
- Page 433 and 434: R:V Register and V Memory Data Move
- Page 435 and 436: R:V Register and Y Memory Data Move
- Page 437 and 438: R:V Register and Y Memory Data Move
- Page 439 and 440: L: Long Memory Data Move L:Example:
- Page 441 and 442: L: Long Memory Data Move L:Instruct
- Page 443 and 444: X: Y: xv Memory Data Move X: Y:Exam
- Page 445 and 446: X: Y: xv Memory Data Move X: Y:S1 D
- Page 447 and 448: MOVEC Move Control Register MOVECst
- Page 449 and 450: MOVEC Move Control Register MOVECCo
- Page 451 and 452: MOVECMove Control RegisterMOVECInst
No Parallel Data MoveOperation:Assembler Syntax:( ..... ) ( ..... )where ( ..... ) refers to any arithmetic or logical instruction which allows parallel moves.Description: Many (30 <strong>of</strong> the total 66) instructions in the DSP56K instruction set allowparallel moves. The parallel moves have been divided into 10 opcode categories. Thiscategory is a parallel move NOP and does not involve data bus move activity.Example:ADD XO,A;add XO to A (no parallel move)Explanation <strong>of</strong> Example: This is an example <strong>of</strong> an instruction which allows parallelmoves but does not have one.Condition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 oI LF I DM I T I - I S1 I SO I 11 I 10 I S I L I E I u N I z~ MR .. III( CCRThe condition codes are affected by the instruction, not the move.-