section 7 - Index of

MOVE Move Data MOVEParallel Move Descriptions: Thirty of the sixty-two instructions allow an optional paralleldata bus movement over the X and/or Y data bus. This allows a data ALU operation tobe executed in parallel with up to two data bus moves during the instruction cycle. Tentypes of parallel moves are permitted, including register to register moves, register tomemory moves, and memory to register moves. However, not all addressing modes areallowed for each type of memory reference. Addressing mode restrictions which apply tospecific types of moves are noted in the individual move operation descriptions. The followingsection contains detailed descriptions about each type of parallel move operation.When a 56-bit accumulator (A or B) is specified as a source operand S, the accumulatorvalue is optionally shifted according to the scaling mode bits SO and S1 in the systemstatus register (SR). If the data out of the shifter indicates that the accumulator extensionregister is in use and the data is to be moved into a 24- or 48-bit destination, the valuestored in the destination D is limited to a maximum positive or negative saturation constantto minimize truncation error. Limiting does not occur if an individual 24-bit accumulatorregister (A1, AD, B1, or BO) is specified as a source operand instead of the full 56-bitaccumulator (A or B). This limiting feature allows block floating-point operations to beperformed with error detection since the L bit in the condition code register is latched.Note: Whenever an instruction uses an accumulator as both a destination operand for adata ALU operation and as a source for a parallel move operation, the parallel moveoperation occurs first and will use the data that exists in the accumulator before theexecution of the data ALU operation has occurred.