section 7 - Index of
section 7 - Index of section 7 - Index of
MOVE Move Data MOVEOperation:S~DAssembler Syntax:MOVE S,DDescription: Move the contents of the specified data source S to the specified destinationD. This instruction is equivalent to a data ALU NOP with a parallel data move.When a 56-bit accumulator (A or B) is specified as a source operand S, the accumulatorvalue is optionally shifted according to the scaling mode bits SO and S 1 in the systemstatus register (SR). If the data out of the shifter indicates that the accumulator extensionregister is in use and the data is to be moved into a 24- or 48-bit destination, the valuestored in the destination D is limited to a maximum positive or negative saturation constantto minimize truncation error. Limiting does not occur if an individual 24-bit accumulatorregister (A1, AO, B1, or BO) is specified as a source operand instead of the full 56-bitaccumulator (A or B). This limiting feature allows block floating-point operations to beperformed with error detection since the L bit in the condition code register is latched.When a 56-bit accumulator (A or B) is specified as a destination operand 0, any 24-bitsource data to be moved into that accumulator is automatically extended to 56 bits bysign extending the MS bit of the source operand (bit 23) and appending the source operandwith 24 LS zeros. Similarly, any 48-bit source data to be loaded into a 56-bit accumulatoris automatically sign extended to 56 bits. Note that for 24-bit source operandsboth the automatic sign-extension and zeroing features may be disabled by specifyingthe destination register to be one of the individual 24-bit accumulator registers (A 1 orB1). Similarly, for 48-bit source operands, the automatic sign-extension feature may bedisabled by using the long memory move addressing mode and specifying A10 or B10 asthe destination operand.Example:MOVE XO,A 1;move XO to A 1 without sign ext. or zeroingxo ~I ________ ~$2_34_5_67 __ ~ xol ~ ________ ~$2_3_45_67 __ ~A I~ __ $F_F_:F_FF_FF_F_:F_FF_F_FF __ ~A ~I ____ $_FF_:2_34_56_7_:F_FF_FF_F __--I
MOVE Move Data MOVEExplanation of Example: Prior to execution, the 56-bit A accumulator contains thevalue $FF:FFFFFF:FFFFFF, and the 24-bit XO register contains the value $234567. Theexecution of the MOVE XO,A 1 instruction moves the 24-bit value in the XO register intothe 24-bit A 1 register without automatic sign extension and without automatic zeroing.Condition Codes:S -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 01 LF I OM I T I .. I S1 I SO I 11... MR ....10 1 s 1 L E I U N Z vCCR 1:1Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if data limiting has occurred during parallel move.Instruction Format:MOVE S,DOpcode:23 8 7 4 3 oDATA BUS MOVE FIELD I 0 o o o I 0 o o oOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:See Parallel Move Descriptions for data bus move field encoding.Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words
- Page 347 and 348: Jcc Jump Conditionally JccRestricti
- Page 349 and 350: JccJump ConditionallyJccEffectiveAd
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
- Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
- Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
- Page 359 and 360: JSccJump to Subroutine Conditionall
- Page 361 and 362: JScc Jump to Subroutine Conditional
- Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
- Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
- Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
- Page 369 and 370: JSCLR Jump to Subroutine If Bit Cle
- Page 371 and 372: JSET Jump if Bit Set JSETRestrictio
- Page 373 and 374: JSETJump if Bit SetJSETInstruction
- Page 375 and 376: JSET Jump If Bit Set JSETInstructio
- Page 377 and 378: JSR Jump to Subroutine JSRInstructi
- Page 379 and 380: JSSET Jump to Subroutine if Bit Set
- Page 381 and 382: JSSETJump to Subroutine if Bit SetJ
- Page 383 and 384: JSSET Jump to Subroutine if Bit Set
- Page 385 and 386: LSL Logical Shift Left LSLCondition
- Page 387 and 388: LSR Logical Shift Right LSRConditio
- Page 389 and 390: LUALoad Updated AddressLUACondition
- Page 391 and 392: MAC Signed Multiply-Accumulate MACC
- Page 393 and 394: MACSigned Multiply-AccumulateMACTim
- Page 395 and 396: MACR Signed Multiply-Accumulate and
- Page 397: MACR Signed MUltiply-Accumulate and
- Page 401 and 402: MOVE Move Data MOVEWhen a 56-bit ac
- Page 403 and 404: No Parallel Data MoveInstruction Fo
- Page 405 and 406: I Immediate Short Data Move IExampl
- Page 407 and 408: I Immediate Short Data Move IDDD d
- Page 409 and 410: R Register to Register Data Move RE
- Page 411 and 412: R Register to Register Data Move RI
- Page 413 and 414: uAddress Register UpdateuInstructio
- Page 415 and 416: X: X Memory Data Move X:Note:Due to
- Page 417 and 418: X: X Memory Data Move X:S D DS,D d
- Page 419 and 420: X: X Memory Data Move X:S D DS,D d
- Page 421 and 422: X:R X Memory and Register Data Move
- Page 423 and 424: X:R X Memory and Register Data Move
- Page 425 and 426: X:R X Memory and Register Data Move
- Page 427 and 428: Y: Y Memory Data Move Y:Note: This
- Page 429 and 430: Y: Y Memory Data Move Y:S D DS,D d
- Page 431 and 432: Y: Y Memory Data Move Y:S D DS,D d
- Page 433 and 434: R:V Register and V Memory Data Move
- Page 435 and 436: R:V Register and Y Memory Data Move
- Page 437 and 438: R:V Register and Y Memory Data Move
- Page 439 and 440: L: Long Memory Data Move L:Example:
- Page 441 and 442: L: Long Memory Data Move L:Instruct
- Page 443 and 444: X: Y: xv Memory Data Move X: Y:Exam
- Page 445 and 446: X: Y: xv Memory Data Move X: Y:S1 D
- Page 447 and 448: MOVEC Move Control Register MOVECst
MOVE Move Data MOVEOperation:S~DAssembler Syntax:MOVE S,DDescription: Move the contents <strong>of</strong> the specified data source S to the specified destinationD. This instruction is equivalent to a data ALU NOP with a parallel data move.When a 56-bit accumulator (A or B) is specified as a source operand S, the accumulatorvalue is optionally shifted according to the scaling mode bits SO and S 1 in the systemstatus register (SR). If the data out <strong>of</strong> the shifter indicates that the accumulator extensionregister is in use and the data is to be moved into a 24- or 48-bit destination, the valuestored in the destination D is limited to a maximum positive or negative saturation constantto minimize truncation error. Limiting does not occur if an individual 24-bit accumulatorregister (A1, AO, B1, or BO) is specified as a source operand instead <strong>of</strong> the full 56-bitaccumulator (A or B). This limiting feature allows block floating-point operations to beperformed with error detection since the L bit in the condition code register is latched.When a 56-bit accumulator (A or B) is specified as a destination operand 0, any 24-bitsource data to be moved into that accumulator is automatically extended to 56 bits bysign extending the MS bit <strong>of</strong> the source operand (bit 23) and appending the source operandwith 24 LS zeros. Similarly, any 48-bit source data to be loaded into a 56-bit accumulatoris automatically sign extended to 56 bits. Note that for 24-bit source operandsboth the automatic sign-extension and zeroing features may be disabled by specifyingthe destination register to be one <strong>of</strong> the individual 24-bit accumulator registers (A 1 orB1). Similarly, for 48-bit source operands, the automatic sign-extension feature may bedisabled by using the long memory move addressing mode and specifying A10 or B10 asthe destination operand.Example:MOVE XO,A 1;move XO to A 1 without sign ext. or zeroingxo ~I ________ ~$2_34_5_67 __ ~ xol ~ ________ ~$2_3_45_67 __ ~A I~ __ $F_F_:F_FF_FF_F_:F_FF_F_FF __ ~A ~I ____ $_FF_:2_34_56_7_:F_FF_FF_F __--I