section 7 - Index of
section 7 - Index of section 7 - Index of
MACR Signed Multiply-Accumulate and Round MACROperation:D±S1 *S2+r.-.D (parallel move)Assembler Syntax:MACR (±)S1,S2,D (parallel move)D±S1 *S2+r.-. D (parallel move)D±(S1 *2- n )+r.-.D (no parallel move)MACRMACR(±)S2,S1,D (parallel move)(±)S,#n,D (no parallel move)Description: Multiply the two signed 24-bit source operands S1 and S2 (or the signed24-bit source operand S by the positive 24-bit immediate operand 2- n ), add/subtract theproduct to/from the specified 56-bit destination accumulator D, and then round the resultusing convergent rounding. The rounded result is stored in the destination accumulatorD.The U_" sign option negates the specified product prior to accumulation. The default signoption is u+".The contribution of the LS bits of the result is rounded into the upper portion of the destinationaccumulator (A1 or B1) by adding a constant to the LS bits of the lower portion ofthe accumulator (AO or BO). The value of the constant added is determined by the scalingmode bits SO and S1 in the status register. Once rounding has been completed, theLS bits of the destination accumulator D (AO or BO) are loaded with zeros to maintain anunbiased accumulator value which may be reused by the next instruction. The upper portionof the accumulator (A1 or B1) contains the rounded result which may be read out tothe data buses. Refer to the RND instruction for more complete information on the convergentrounding process.Example 1:MACR XO,YO,B B,XO Y:(R4)+N4,YO ;XO*YO+B'-'B, and B, update XO,YO,R4Before ExecutionAfter ExecutionXO I $123456 XO I $100000YO I $123456 YO I $987654B I $00:100000:000000 B I $00:1296CE:000000
MACR Signed Multiply-Accumulate and Round MACRExplanation of Example 1: Prior to execution, the 24-bit XO register contains the value$123456 (0.142222166), the 24-bit YO register contains the value $123456(0.142222166), and the 56-bit B accumulator contains the value $00:100000:000000(0.125). The execution of the MACR XO,YO,B instruction multiples the 24-bit signed valuein the XO register by the 24-bit signed value in the YO register, adds the resulting productto the 56-bit B accumulator, rounds the result into the B1 portion of the accumulator, andthen zeros the BO portion of the accumulator (XO*YO+B=0.145227144519197 approximately=$00:1296CD:9619C8, which is rounded to the value$00:1296CE:000000=0.145227193832397=B).Condition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0IlF I DM I T I.. I S1 I SO I 11 I 10 I s I L E I u I N I z vCCA I ~I41( MA .....S - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if limiting (parallel move) or overflow has occurred in resultE - Set if the signed integer portion of A or B result is in useU - Set if A or B result is unnormalizedN - Set if bit 55 of A or B result is setZ- Set if A or B result equals zeroV - Set if overflow has occurred in A or B resultNote: The definitions of the E and U bits vary according to the scaling mode being used.Refer to Section A.5 for complete details.Instruction Format 1:MACR (±)S1,S2,0MACR (±)S2,S 1 ,0Opcode 1:23DATA BUS MOVE FIELD8 7 4 3I 1 Q Q Q I d kOPTIONAL EFFECTIVE ADDRESS EXTENSIONo
- Page 343 and 344: ILLEGALIllegal Instruction Interrup
- Page 345 and 346: INC Increment by One INCInstruction
- Page 347 and 348: Jcc Jump Conditionally JccRestricti
- Page 349 and 350: JccJump ConditionallyJccEffectiveAd
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
- Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
- Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
- Page 359 and 360: JSccJump to Subroutine Conditionall
- Page 361 and 362: JScc Jump to Subroutine Conditional
- Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
- Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
- Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
- Page 369 and 370: JSCLR Jump to Subroutine If Bit Cle
- Page 371 and 372: JSET Jump if Bit Set JSETRestrictio
- Page 373 and 374: JSETJump if Bit SetJSETInstruction
- Page 375 and 376: JSET Jump If Bit Set JSETInstructio
- Page 377 and 378: JSR Jump to Subroutine JSRInstructi
- Page 379 and 380: JSSET Jump to Subroutine if Bit Set
- Page 381 and 382: JSSETJump to Subroutine if Bit SetJ
- Page 383 and 384: JSSET Jump to Subroutine if Bit Set
- Page 385 and 386: LSL Logical Shift Left LSLCondition
- Page 387 and 388: LSR Logical Shift Right LSRConditio
- Page 389 and 390: LUALoad Updated AddressLUACondition
- Page 391 and 392: MAC Signed Multiply-Accumulate MACC
- Page 393: MACSigned Multiply-AccumulateMACTim
- Page 397 and 398: MACR Signed MUltiply-Accumulate and
- Page 399 and 400: MOVE Move Data MOVEExplanation of E
- Page 401 and 402: MOVE Move Data MOVEWhen a 56-bit ac
- Page 403 and 404: No Parallel Data MoveInstruction Fo
- Page 405 and 406: I Immediate Short Data Move IExampl
- Page 407 and 408: I Immediate Short Data Move IDDD d
- Page 409 and 410: R Register to Register Data Move RE
- Page 411 and 412: R Register to Register Data Move RI
- Page 413 and 414: uAddress Register UpdateuInstructio
- Page 415 and 416: X: X Memory Data Move X:Note:Due to
- Page 417 and 418: X: X Memory Data Move X:S D DS,D d
- Page 419 and 420: X: X Memory Data Move X:S D DS,D d
- Page 421 and 422: X:R X Memory and Register Data Move
- Page 423 and 424: X:R X Memory and Register Data Move
- Page 425 and 426: X:R X Memory and Register Data Move
- Page 427 and 428: Y: Y Memory Data Move Y:Note: This
- Page 429 and 430: Y: Y Memory Data Move Y:S D DS,D d
- Page 431 and 432: Y: Y Memory Data Move Y:S D DS,D d
- Page 433 and 434: R:V Register and V Memory Data Move
- Page 435 and 436: R:V Register and Y Memory Data Move
- Page 437 and 438: R:V Register and Y Memory Data Move
- Page 439 and 440: L: Long Memory Data Move L:Example:
- Page 441 and 442: L: Long Memory Data Move L:Instruct
- Page 443 and 444: X: Y: xv Memory Data Move X: Y:Exam
MACR Signed Multiply-Accumulate and Round MACROperation:D±S1 *S2+r.-.D (parallel move)Assembler Syntax:MACR (±)S1,S2,D (parallel move)D±S1 *S2+r.-. D (parallel move)D±(S1 *2- n )+r.-.D (no parallel move)MACRMACR(±)S2,S1,D (parallel move)(±)S,#n,D (no parallel move)Description: Multiply the two signed 24-bit source operands S1 and S2 (or the signed24-bit source operand S by the positive 24-bit immediate operand 2- n ), add/subtract theproduct to/from the specified 56-bit destination accumulator D, and then round the resultusing convergent rounding. The rounded result is stored in the destination accumulatorD.The U_" sign option negates the specified product prior to accumulation. The default signoption is u+".The contribution <strong>of</strong> the LS bits <strong>of</strong> the result is rounded into the upper portion <strong>of</strong> the destinationaccumulator (A1 or B1) by adding a constant to the LS bits <strong>of</strong> the lower portion <strong>of</strong>the accumulator (AO or BO). The value <strong>of</strong> the constant added is determined by the scalingmode bits SO and S1 in the status register. Once rounding has been completed, theLS bits <strong>of</strong> the destination accumulator D (AO or BO) are loaded with zeros to maintain anunbiased accumulator value which may be reused by the next instruction. The upper portion<strong>of</strong> the accumulator (A1 or B1) contains the rounded result which may be read out tothe data buses. Refer to the RND instruction for more complete information on the convergentrounding process.Example 1:MACR XO,YO,B B,XO Y:(R4)+N4,YO ;XO*YO+B'-'B, and B, update XO,YO,R4Before ExecutionAfter ExecutionXO I $123456 XO I $100000YO I $123456 YO I $987654B I $00:100000:000000 B I $00:1296CE:000000
Change language