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LSR Logical Shift Right LSRCondition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I: IOMI T 1**J:, I S0 '1111~I.. s I LIE I UceRN I z v 1:.1S - Computed according to the definition in A.S CONDITION CODE COMPUTATIONL - Set if data limiting has occurred during parallel moveN - Always clearedZ- Set if bits 47-24 <strong>of</strong> A or B result are zeroV - Always clearedC - Set if bit 24 <strong>of</strong> A or B was set prior to Instruction executionInstruction Format:LSR DOpcode:23 8 7DATA BUS MOVE FIELD I 0 0OPTIONAL EFFECTIVE ADDRESS EXTENSION4 3Old 0oInstruction Fields:DdADB 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words

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