section 7 - Index of
section 7 - Index of section 7 - Index of
LSR Logical Shift Right LSROperation:47 24O~ I -----I.~ I ~ C (parallel move)Assembler Syntax:LSR D (parallel move)Description: Logically shift bits 47-24 of the destination operand D one bit to the rightand store the result in the destination accumulator. Prior to instruction execution, bit 24 ofD is shifted into the carry bit C, and a zero is shifted into bit 47 of the destination accumulatorD. This instruction is a 24-bit operation. The remaining bits of the destination operandD are not affected.Example:LSR A 1 A 1, N4 ;shift A 1 one bit to the right, set up N4Before ExecutionA ~I ___ $3_7:_44_44_45_:8_28_1_80 __ ~SRI ~ ______ $_03_00_~After ExecutionA 1'--_$_37_:2_22_22_2:_82_81_80_---'SR~I ________ $0_3_01_---'Explanation of Example: Prior to execution, the 56-bit A accumulator contains thevalue $37:444445:828180. The execution of the LSR A instruction shifts the 24-bit valuein the A1 register one bit to the right and stores the result back in the A1 register.
LSR Logical Shift Right LSRCondition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I: IOMI T 1**J:, I S0 '1111~I.. s I LIE I UceRN I z v 1:.1S - Computed according to the definition in A.S CONDITION CODE COMPUTATIONL - Set if data limiting has occurred during parallel moveN - Always clearedZ- Set if bits 47-24 of A or B result are zeroV - Always clearedC - Set if bit 24 of A or B was set prior to Instruction executionInstruction Format:LSR DOpcode:23 8 7DATA BUS MOVE FIELD I 0 0OPTIONAL EFFECTIVE ADDRESS EXTENSION4 3Old 0oInstruction Fields:DdADB 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
- Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
- Page 341 and 342: EOR Logical Exclusive OR EORInstruc
- Page 343 and 344: ILLEGALIllegal Instruction Interrup
- Page 345 and 346: INC Increment by One INCInstruction
- Page 347 and 348: Jcc Jump Conditionally JccRestricti
- Page 349 and 350: JccJump ConditionallyJccEffectiveAd
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
- Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
- Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
- Page 359 and 360: JSccJump to Subroutine Conditionall
- Page 361 and 362: JScc Jump to Subroutine Conditional
- Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
- Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
- Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
- Page 369 and 370: JSCLR Jump to Subroutine If Bit Cle
- Page 371 and 372: JSET Jump if Bit Set JSETRestrictio
- Page 373 and 374: JSETJump if Bit SetJSETInstruction
- Page 375 and 376: JSET Jump If Bit Set JSETInstructio
- Page 377 and 378: JSR Jump to Subroutine JSRInstructi
- Page 379 and 380: JSSET Jump to Subroutine if Bit Set
- Page 381 and 382: JSSETJump to Subroutine if Bit SetJ
- Page 383 and 384: JSSET Jump to Subroutine if Bit Set
- Page 385: LSL Logical Shift Left LSLCondition
- Page 389 and 390: LUALoad Updated AddressLUACondition
- Page 391 and 392: MAC Signed Multiply-Accumulate MACC
- Page 393 and 394: MACSigned Multiply-AccumulateMACTim
- Page 395 and 396: MACR Signed Multiply-Accumulate and
- Page 397 and 398: MACR Signed MUltiply-Accumulate and
- Page 399 and 400: MOVE Move Data MOVEExplanation of E
- Page 401 and 402: MOVE Move Data MOVEWhen a 56-bit ac
- Page 403 and 404: No Parallel Data MoveInstruction Fo
- Page 405 and 406: I Immediate Short Data Move IExampl
- Page 407 and 408: I Immediate Short Data Move IDDD d
- Page 409 and 410: R Register to Register Data Move RE
- Page 411 and 412: R Register to Register Data Move RI
- Page 413 and 414: uAddress Register UpdateuInstructio
- Page 415 and 416: X: X Memory Data Move X:Note:Due to
- Page 417 and 418: X: X Memory Data Move X:S D DS,D d
- Page 419 and 420: X: X Memory Data Move X:S D DS,D d
- Page 421 and 422: X:R X Memory and Register Data Move
- Page 423 and 424: X:R X Memory and Register Data Move
- Page 425 and 426: X:R X Memory and Register Data Move
- Page 427 and 428: Y: Y Memory Data Move Y:Note: This
- Page 429 and 430: Y: Y Memory Data Move Y:S D DS,D d
- Page 431 and 432: Y: Y Memory Data Move Y:S D DS,D d
- Page 433 and 434: R:V Register and V Memory Data Move
- Page 435 and 436: R:V Register and Y Memory Data Move
LSR Logical Shift Right LSROperation:47 24O~ I -----I.~ I ~ C (parallel move)Assembler Syntax:LSR D (parallel move)Description: Logically shift bits 47-24 <strong>of</strong> the destination operand D one bit to the rightand store the result in the destination accumulator. Prior to instruction execution, bit 24 <strong>of</strong>D is shifted into the carry bit C, and a zero is shifted into bit 47 <strong>of</strong> the destination accumulatorD. This instruction is a 24-bit operation. The remaining bits <strong>of</strong> the destination operandD are not affected.Example:LSR A 1 A 1, N4 ;shift A 1 one bit to the right, set up N4Before ExecutionA ~I ___ $3_7:_44_44_45_:8_28_1_80 __ ~SRI ~ ______ $_03_00_~After ExecutionA 1'--_$_37_:2_22_22_2:_82_81_80_---'SR~I ________ $0_3_01_---'Explanation <strong>of</strong> Example: Prior to execution, the 56-bit A accumulator contains thevalue $37:444445:828180. The execution <strong>of</strong> the LSR A instruction shifts the 24-bit valuein the A1 register one bit to the right and stores the result back in the A1 register.
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