section 7 - Index of
section 7 - Index of section 7 - Index of
JScc Jump to Subroutine Conditionally JSccInstruction Format:JScc xxxOpcode:23 16 15 8 7 o10 0 0 0 1 1 1 a a a a a a 81Instruction Fields:cc=4-bit condition code=CCCC,xxx=12-bit Short Jump Address=aaaaaaaaaaaaMnemonic C C C C Mnemonic C C C CCC (HS) 0 0 0 0 CS (LO) 0 0 0GE 0 0 0 1 LT 0 0 1NE 0 0 1 0 EQ 0 1 0PL 0 0 1 1 MI 0 1 1NN 0 1 0 0 NR 1 0 0EC 0 1 0 1 ES 1 0 1LC 0 1 1 0 LS 1 1 0GT 0 1 1 1 LE 1 1 1Timing: 4+jx oscillator clock cyclesMemory: 1 +ea program words-
JScc Jump to Subroutine Conditionally JSccInstruction Format:JScc eaOpcode:23 16 15· 8 7 00000101 M MMRRRI1 0 10 CCCCOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:cc=4-bit condition code=CCCC,ea=6-bit Effective Address=MMMRRREffectiveAddressing Mode M M M R R R(Rn)-Nn 000 r r r CC (HS)(Rn)+NnO 001 r r r GE(Rn)- 010 r r NE(Rn)+ o 1 1 r r PL(Rn) 100 r r NN(Rn+Nn) 1 0 1 r r EC-(Rn) 1 1 1 r r r LCAbsolute address 1 1 000 0 GTwhere "rrr" refers to an address register RO-R7Timing: 4+jx oscillator clock cyclesMemory: 1 +ea program wordsMnemonic C C C Co 0 0 0o 0 0 1o 0 1 0o 0 1 1o 1 0 0o 1 0 1o 1 1 0011 1Mnemonic C C CCS (LO) 100LT 100EQ 1 0 1MI 1 0 1NR 1 1 0ES 1 1 0LS 1 1 1LE 1 1 1C01010101-
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
- Page 325 and 326: DIV Divide Interation DIVNote that
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
- Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
- Page 341 and 342: EOR Logical Exclusive OR EORInstruc
- Page 343 and 344: ILLEGALIllegal Instruction Interrup
- Page 345 and 346: INC Increment by One INCInstruction
- Page 347 and 348: Jcc Jump Conditionally JccRestricti
- Page 349 and 350: JccJump ConditionallyJccEffectiveAd
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
- Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
- Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
- Page 359: JSccJump to Subroutine Conditionall
- Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
- Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
- Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
- Page 369 and 370: JSCLR Jump to Subroutine If Bit Cle
- Page 371 and 372: JSET Jump if Bit Set JSETRestrictio
- Page 373 and 374: JSETJump if Bit SetJSETInstruction
- Page 375 and 376: JSET Jump If Bit Set JSETInstructio
- Page 377 and 378: JSR Jump to Subroutine JSRInstructi
- Page 379 and 380: JSSET Jump to Subroutine if Bit Set
- Page 381 and 382: JSSETJump to Subroutine if Bit SetJ
- Page 383 and 384: JSSET Jump to Subroutine if Bit Set
- Page 385 and 386: LSL Logical Shift Left LSLCondition
- Page 387 and 388: LSR Logical Shift Right LSRConditio
- Page 389 and 390: LUALoad Updated AddressLUACondition
- Page 391 and 392: MAC Signed Multiply-Accumulate MACC
- Page 393 and 394: MACSigned Multiply-AccumulateMACTim
- Page 395 and 396: MACR Signed Multiply-Accumulate and
- Page 397 and 398: MACR Signed MUltiply-Accumulate and
- Page 399 and 400: MOVE Move Data MOVEExplanation of E
- Page 401 and 402: MOVE Move Data MOVEWhen a 56-bit ac
- Page 403 and 404: No Parallel Data MoveInstruction Fo
- Page 405 and 406: I Immediate Short Data Move IExampl
- Page 407 and 408: I Immediate Short Data Move IDDD d
- Page 409 and 410: R Register to Register Data Move RE
JScc Jump to Subroutine Conditionally JSccInstruction Format:JScc eaOpcode:23 16 15· 8 7 00000101 M MMRRRI1 0 10 CCCCOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:cc=4-bit condition code=CCCC,ea=6-bit Effective Address=MMMRRREffectiveAddressing Mode M M M R R R(Rn)-Nn 000 r r r CC (HS)(Rn)+NnO 001 r r r GE(Rn)- 010 r r NE(Rn)+ o 1 1 r r PL(Rn) 100 r r NN(Rn+Nn) 1 0 1 r r EC-(Rn) 1 1 1 r r r LCAbsolute address 1 1 000 0 GTwhere "rrr" refers to an address register RO-R7Timing: 4+jx oscillator clock cyclesMemory: 1 +ea program wordsMnemonic C C C Co 0 0 0o 0 0 1o 0 1 0o 0 1 1o 1 0 0o 1 0 1o 1 1 0011 1Mnemonic C C CCS (LO) 100LT 100EQ 1 0 1MI 1 0 1NR 1 1 0ES 1 1 0LS 1 1 1LE 1 1 1C01010101-
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