section 7 - Index of
section 7 - Index of section 7 - Index of
EOR Logical Exclusive OR EOROperation:S E9 0[47:24] -+0[47:24] (parallel move)Assembler Syntax:EOR S,O (parallel move)where E9 denotes the logical Exclusive OR operatorDescription: Logically exclusive OR the source operand S with bits 47-24 of the destinationoperand 0 and store the result in bits 47-24 of the destination accumulator. Thisinstruction is a 24-bit operation. The remaining bits of the destination operand 0 are notaffected.Example:EOR Y1 ,81 (R2)+ ;Exclusive OR Y1 with 81, update R2Y1Before Execution1~ _______After Execution$_00_00_0_3 __ ~ Y1 1~ ________ $_0_00_00_3 __ ~B 1~ __ $_00_:0_00_0_05_:0_00_00_0 __ ~B l-I ____ $0_0_:00_00_0_6:0_0_00_00 __---'Explanation of Example: Prior to execution, the 24-bit Y1 register contains the value$000003, and the 56-bit 8 accumulator contains the value $00:000005:000000. TheEOR Y1 ,8 instruction logically exclusive ORs the 24-bit value in the Y1 register with bits47-24 of the 8 accumulator (81) and stores the result in the 8 accumulator with bits 55-48 and 23-0 unchanged.Condition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2I LF 1 DM 1 T 1** 181 180 1 11 1 10 I s I L I E I u N I z... MR • III( CCR°S - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if data limiting has occurred during parallel moveN - Set if bit 47 of A or B result is setZ- Set if bits 47 - 24 of A or B result are zeroV - Always cleared
EOR Logical Exclusive OR EORInstruction Format:EOR S,DOpcode:23 8 7 4 3 oDATA BUS MOVE FIELD I 0 J J I d 0OPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:S JJ 0 dXO 00 A 0X1 1 0 B 1YO 01Y1 1 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words-
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
- Page 325 and 326: DIV Divide Interation DIVNote that
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
- Page 339: ENDDO End Current DO Loop ENDDOExpl
- Page 343 and 344: ILLEGALIllegal Instruction Interrup
- Page 345 and 346: INC Increment by One INCInstruction
- Page 347 and 348: Jcc Jump Conditionally JccRestricti
- Page 349 and 350: JccJump ConditionallyJccEffectiveAd
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
- Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
- Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
- Page 359 and 360: JSccJump to Subroutine Conditionall
- Page 361 and 362: JScc Jump to Subroutine Conditional
- Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
- Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
- Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
- Page 369 and 370: JSCLR Jump to Subroutine If Bit Cle
- Page 371 and 372: JSET Jump if Bit Set JSETRestrictio
- Page 373 and 374: JSETJump if Bit SetJSETInstruction
- Page 375 and 376: JSET Jump If Bit Set JSETInstructio
- Page 377 and 378: JSR Jump to Subroutine JSRInstructi
- Page 379 and 380: JSSET Jump to Subroutine if Bit Set
- Page 381 and 382: JSSETJump to Subroutine if Bit SetJ
- Page 383 and 384: JSSET Jump to Subroutine if Bit Set
- Page 385 and 386: LSL Logical Shift Left LSLCondition
- Page 387 and 388: LSR Logical Shift Right LSRConditio
- Page 389 and 390: LUALoad Updated AddressLUACondition
EOR Logical Exclusive OR EOROperation:S E9 0[47:24] -+0[47:24] (parallel move)Assembler Syntax:EOR S,O (parallel move)where E9 denotes the logical Exclusive OR operatorDescription: Logically exclusive OR the source operand S with bits 47-24 <strong>of</strong> the destinationoperand 0 and store the result in bits 47-24 <strong>of</strong> the destination accumulator. Thisinstruction is a 24-bit operation. The remaining bits <strong>of</strong> the destination operand 0 are notaffected.Example:EOR Y1 ,81 (R2)+ ;Exclusive OR Y1 with 81, update R2Y1Before Execution1~ _______After Execution$_00_00_0_3 __ ~ Y1 1~ ________ $_0_00_00_3 __ ~B 1~ __ $_00_:0_00_0_05_:0_00_00_0 __ ~B l-I ____ $0_0_:00_00_0_6:0_0_00_00 __---'Explanation <strong>of</strong> Example: Prior to execution, the 24-bit Y1 register contains the value$000003, and the 56-bit 8 accumulator contains the value $00:000005:000000. TheEOR Y1 ,8 instruction logically exclusive ORs the 24-bit value in the Y1 register with bits47-24 <strong>of</strong> the 8 accumulator (81) and stores the result in the 8 accumulator with bits 55-48 and 23-0 unchanged.Condition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2I LF 1 DM 1 T 1** 181 180 1 11 1 10 I s I L I E I u N I z... MR • III( CCR°S - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if data limiting has occurred during parallel moveN - Set if bit 47 <strong>of</strong> A or B result is setZ- Set if bits 47 - 24 <strong>of</strong> A or B result are zeroV - Always cleared