section 7 - Index of
section 7 - Index of section 7 - Index of
DIV Divide Interation DIVExample: (4-Quadrant division, 24-bit signed quotient, 48-blt signed remainder)ABS A A,B;make dividend positive, copy A1 to B1EOR XO,B B,X:$O ;save rem. sign in X:$O, quo. sign in NAND #$FE,CCR ;clear carry bit C (quotient sign bit)REP #$18;form a 24-bit quotientDIV XO,A;form quotient in AO, remainder in A1TFR A,B;save quotient and remainder in B1,BOJPL SAVEQUO;go to SAVEQUO if quotient is positiveNEG 8;complement quotient if N bit setSAVEQUO TFR XO,B BO,X1;save quo. in X1, get signed divisorA8S B;get absolute value of signed divisorADD A,B;restore remainder in B1JCLR #23,X:$O,DONE ;go to DONE if remainder is positiveMOVE #$0,80 ;clear LS 24 bits of 8NEG B;complement remainder if negativeDONE .......Before ExecutionAfter ExecutionAI$00:OE66D7:F2832C AI$FF:EDCCAA:654321XO I $123456 XO I $123456X1I$000000 X1I$654321BI$00:000000:000000 BI$00:000100:654321-Explanation of Example: Prior to execution, the 56-bit A accumulator contains the 56-bit, sign-extended fractional dividend D (D=$00.OE66D7:F2832C=0.112513535894635approx.) and the 24-bit XO register contains the 24-bit, signed fractional divisor S(S=$123456=0.142222166061401). Since IDI
DIV Divide Interation DIVNote that the divide routine used in the previous example assumes that the signextended56-bit signed fractional dividend is stored in the A accumulator and that the 24-bit signed fractional divisor is stored in the XO register. This routine produces a full 24-bitsigned quotient and a 48-bit signed remainder.This routine may be greatly simplified for the case in which only positive, fractional operandsare used to produce a 24-bit positive quotient and a 48-bit positive remainder, asshown in the following example:1-Quadrant division, 24-bit unsigned quotient, 48-bit unsigned remainderAND #$FE,CCR ;clear carry bit C (quotient sign bit)REP #$18;form a 24-bit quotient and remainderDIV XO,A;form quotient in AO, remainder in A1ADD XO,A;restore remainder in A1Note that this routine assumes that the 56-bit positive, fractional, sign-extended dividendis stored in the A accumulator and that the 24-bit positive, fractional divisor is stored inthe XO register. After execution, the 24-bit positive fractional quotient is stored in the AOregister; the LS 24 bits of the 48-bit positive fractional remainder are stored in the A 1 register.There are many variations possible when choosing a suitable division routine for a givenapplication. The selection of a suitable division routine normally involves specification ofthe following items:1. the number of bits of precision in the dividend;2. the number of bits of precision N in the quotient;3. whether the value of N is fixed or is variable;4. whether the operands are unsigned or signed;5. whether or not the remainder is to be calculated.
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323: DIV Divide Interation DIVThe DIV in
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
- Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
- Page 341 and 342: EOR Logical Exclusive OR EORInstruc
- Page 343 and 344: ILLEGALIllegal Instruction Interrup
- Page 345 and 346: INC Increment by One INCInstruction
- Page 347 and 348: Jcc Jump Conditionally JccRestricti
- Page 349 and 350: JccJump ConditionallyJccEffectiveAd
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
- Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
- Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
- Page 359 and 360: JSccJump to Subroutine Conditionall
- Page 361 and 362: JScc Jump to Subroutine Conditional
- Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
- Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
- Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
- Page 369 and 370: JSCLR Jump to Subroutine If Bit Cle
- Page 371 and 372: JSET Jump if Bit Set JSETRestrictio
- Page 373 and 374: JSETJump if Bit SetJSETInstruction
DIV Divide Interation DIVExample: (4-Quadrant division, 24-bit signed quotient, 48-blt signed remainder)ABS A A,B;make dividend positive, copy A1 to B1EOR XO,B B,X:$O ;save rem. sign in X:$O, quo. sign in NAND #$FE,CCR ;clear carry bit C (quotient sign bit)REP #$18;form a 24-bit quotientDIV XO,A;form quotient in AO, remainder in A1TFR A,B;save quotient and remainder in B1,BOJPL SAVEQUO;go to SAVEQUO if quotient is positiveNEG 8;complement quotient if N bit setSAVEQUO TFR XO,B BO,X1;save quo. in X1, get signed divisorA8S B;get absolute value <strong>of</strong> signed divisorADD A,B;restore remainder in B1JCLR #23,X:$O,DONE ;go to DONE if remainder is positiveMOVE #$0,80 ;clear LS 24 bits <strong>of</strong> 8NEG B;complement remainder if negativeDONE .......Before ExecutionAfter ExecutionAI$00:OE66D7:F2832C AI$FF:EDCCAA:654321XO I $123456 XO I $123456X1I$000000 X1I$654321BI$00:000000:000000 BI$00:000100:654321-Explanation <strong>of</strong> Example: Prior to execution, the 56-bit A accumulator contains the 56-bit, sign-extended fractional dividend D (D=$00.OE66D7:F2832C=0.112513535894635approx.) and the 24-bit XO register contains the 24-bit, signed fractional divisor S(S=$123456=0.142222166061401). Since IDI
Change language