section 7 - Index of
section 7 - Index of section 7 - Index of
DEBUGcc Enter Debug Mode Conditionally DEB U G ccOperation:If cc, then enter the debug modeAssembler Syntax:DEBUGccDescription: If the specified condition is true, enter the debug mode and wait for OnCEcommands. If the specified condition is false, continue with the next instruction.The term "cc" may specify the following conditions:CC (HS)CS (LO)ECEQESGEGTLCLELSLTMINENRPLNN"cc" Mnemonic- carry clear (higher or same)- carry set (lower)- extension clear- equal- extension set- greater than or equal- greater than-limit clear- less than or equal-limit set-less than- minus- not equal- normalized-plus- not normalizedConditionC=OC=1E=OZ=1E=1NEB V=OZ+(N EB V)=OL=OZ+(N EB V)=1L=1NEB V=1N=1Z=OZ+(U-E)=1N=OZ+(U-E)=O-whereU denotes the logical complement of U,+ denotes the logical OR operator,- denotes the logical AND operator, andEB denotes the logical Exclusive OR operatorCondition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2I LF I OM I T I ** I SI I SO I 11 I 10 I s I L I E I U N I z I v... MR .. ... CCRThe condition codes are not affected by this instruction.o
DEBUGcc Enter Debug Mode Conditionally DEB U G ccExample:CMP YO, BDEBUGge; Compare register YO with the B accumulator.; Enter the debug mode if; the previous test result is "greater than".Explanation of Example: The results of the comparison between YO and B will berecorded in the status register bits. The conditional debug instruction looks at the conditions(for greater than or equal in this case) and if they are met (N ffi V=O) then theDEBUG instruction will be executed. The chip enters the debug mode after the instructionfollowing the DEBUG instruction has entered the instruction latch. The chip pulseslow the DSO line to inform the external command controller that it has entered the debugmode and that the chip is waiting for commands.Instruction Format:DEBUGccOpcode:23 16 15 8 7 010 0 0 o 0 0 0 o I 0 0 0 0 0 0 1 1 I 0 0 0 0 c c c c IInstruction Fields:Mnemonic c c c c Mnemonic c c c cCC (HS) 0 0 0 0 CS (LO) 0 0 0GE 0 0 0 1 LT 0 0 1NE 0 0 1 0 EQ 0 1 0PL 0 0 1 1 MI 0 1 1NN 0 1 0 0 NR 1 0 0EC 0 1 0 1 ES 1 0 1LC 0 1 1 0 LS 1 1 0GT 0 1 1 1 LE 1 1 1Timing: 4 oscillator clock cyclesMemory: 1 program word
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
- Page 325 and 326: DIV Divide Interation DIVNote that
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
- Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
- Page 341 and 342: EOR Logical Exclusive OR EORInstruc
- Page 343 and 344: ILLEGALIllegal Instruction Interrup
- Page 345 and 346: INC Increment by One INCInstruction
- Page 347 and 348: Jcc Jump Conditionally JccRestricti
- Page 349 and 350: JccJump ConditionallyJccEffectiveAd
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
- Page 355 and 356: JCLR Jump If Bit Clear JCLRInstruct
- Page 357 and 358: JMPJumpJMPInstruction Fields:xxx=12
- Page 359 and 360: JSccJump to Subroutine Conditionall
- Page 361 and 362: JScc Jump to Subroutine Conditional
- Page 363 and 364: JSCLR Jump to Subroutine if Bit Cle
- Page 365 and 366: JSCLRJump to Subroutine If Bit Clea
- Page 367 and 368: JSCLRJump to Subroutine If Bit Clea
DEBUGcc Enter Debug Mode Conditionally DEB U G ccOperation:If cc, then enter the debug modeAssembler Syntax:DEBUGccDescription: If the specified condition is true, enter the debug mode and wait for OnCEcommands. If the specified condition is false, continue with the next instruction.The term "cc" may specify the following conditions:CC (HS)CS (LO)ECEQESGEGTLCLELSLTMINENRPLNN"cc" Mnemonic- carry clear (higher or same)- carry set (lower)- extension clear- equal- extension set- greater than or equal- greater than-limit clear- less than or equal-limit set-less than- minus- not equal- normalized-plus- not normalizedConditionC=OC=1E=OZ=1E=1NEB V=OZ+(N EB V)=OL=OZ+(N EB V)=1L=1NEB V=1N=1Z=OZ+(U-E)=1N=OZ+(U-E)=O-whereU denotes the logical complement <strong>of</strong> U,+ denotes the logical OR operator,- denotes the logical AND operator, andEB denotes the logical Exclusive OR operatorCondition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2I LF I OM I T I ** I SI I SO I 11 I 10 I s I L I E I U N I z I v... MR .. ... CCRThe condition codes are not affected by this instruction.o
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