section 7 - Index of
section 7 - Index of section 7 - Index of
8TST Bit Test 8TSTOperation:Assembler Syntax:D[n] -+ C; BTST #n,X:eaD[n] -+ C; BTST #n,X:aaD[n] -+ C; BTST #n,X:ppD[n] -+ C; BTST #n,Y:eaD[n] -+ C; BTST #n,Y:aaD[n] -+ C; BTST #n,Y:ppD[n] -+ C; BTST #n,DDescription: Test the nth bit of the destination operand D. The state of the nth bit isstored in the carry bit C of the condition code register. The bit to be tested is selected byan immediate bit number from 0-23. This instruction is useful for performing serial to parallelconversion when used with the appropriate rotate instructions. This instruction canuse all memory alterable addressing modes.Example:BTSTROL#$O,X:«$FFEEA;read SSI serial input flag IF1 into C bit;rotate carry bit C into LSB of A 1X:$FFEE 1-1Before Execution___-'-$o_o_oo_o2__---'After ExecutionX:$FFEE 1'--___ $_00_00_02 __--'SR~I ___ ~$_03_00 ____ ---'SRI'--___ ~$_03_01 ____ --'Explanation of Example: Prior to execution, the 24-bit X location X:$FFEE (1/0 SSI statusregister) contains the value $000002. The execution of the BTST #$1,X:«$FFEEinstruction tests the state of the 1 st bit (serial input flag IF1) in X:$FFEE and sets thecarry bit C accordingly. This instruction sequence illustrates serial to parallel conversionusing the carry bit C and the 24-bit A1 register.
BTSTBit TestBTSTCondition Codes:115 14 13 12 11 10 9 8 7 6 5 4 3LF I OM I T I ** I 61 I 60 I 11~ MR ....I lois I L I E I u I N ICCR Condition Codes:For destination operand A or B:C - Set If bit tested Is set. Cleared otherwise.V - Not affectedZ - Not affectedN - Not affectedU - Not affectedE - Not affectedL - Set If data limiting has occurred. See Notes on page A-69.S - Computed according to the definition. See Notes on page A-69.For other destination operands:C - Set H bit tested is set. Cleared otherwise.V - Not affectedZ - Not affectedN - Not affectedU - Not affectedE - Not affectedL - Not affectedS - Not affectedMR Status bits are not affected.CCR2z I v0I :1SP -Stack Pointer:For destination operand SSH: SP - Decrement by 1 .For other destination operands: Not affected
- Page 253 and 254: The address register indirect addre
- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
- Page 259 and 260: Table A-5 Condition Code Computatio
- Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
- Page 263 and 264: ABSAbsolute ValueABSInstruction For
- Page 265 and 266: ADC Add Long with Carry ADCresult.
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303: BSET Bit Test and Set BSETNotes: If
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
- Page 325 and 326: DIV Divide Interation DIVNote that
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
- Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
- Page 341 and 342: EOR Logical Exclusive OR EORInstruc
- Page 343 and 344: ILLEGALIllegal Instruction Interrup
- Page 345 and 346: INC Increment by One INCInstruction
- Page 347 and 348: Jcc Jump Conditionally JccRestricti
- Page 349 and 350: JccJump ConditionallyJccEffectiveAd
- Page 351 and 352: JCLR Jump If Bit Clear JCLRRestrict
- Page 353 and 354: JCLRJump If Bit ClearJCLRInstructio
BTSTBit TestBTSTCondition Codes:115 14 13 12 11 10 9 8 7 6 5 4 3LF I OM I T I ** I 61 I 60 I 11~ MR ....I lois I L I E I u I N ICCR Condition Codes:For destination operand A or B:C - Set If bit tested Is set. Cleared otherwise.V - Not affectedZ - Not affectedN - Not affectedU - Not affectedE - Not affectedL - Set If data limiting has occurred. See Notes on page A-69.S - Computed according to the definition. See Notes on page A-69.For other destination operands:C - Set H bit tested is set. Cleared otherwise.V - Not affectedZ - Not affectedN - Not affectedU - Not affectedE - Not affectedL - Not affectedS - Not affectedMR Status bits are not affected.CCR2z I v0I :1SP -Stack Pointer:For destination operand SSH: SP - Decrement by 1 .For other destination operands: Not affected
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