section 7 - Index of

More documents

Recommendations

Info

BSETBit Test and SetBSETInstruction Format:BSET #n,X:aaBSET #n,Y:aaOpcode:23 16 15 8 710 0 0 0 1 0 1 o I 01 0 a a a a a a I 0oS 1 b b b b blInstruction Fields:#n=bit number=bbbbb,aa=6-bit Absolute Short Address=aaaaaaAbsolute Short Address aaaaaa000000•111111Timing: 4+mvb oscillator clock cyclesMemory: 1 +ea program wordsMemory SpaceSX Memory 0Y Memory 1Bit Number bbbbb00000•10111
BSETBit Test and SetBSETInstruction Format:BSET #n,X:ppBSET #n,Y:ppOpcode:23 16 15 8 710 0 0 0 1 0 1Instruction Fields:#n=bit number=bbbbb,ea=6-bit liD Short Address=pppppp1/0 Short Address pppppp000000•111111Memory SpaceSX MemoryY MemoryaoS 1 b b b b blBit Number bbbbb00000•10111Timing: 4+mvb oscillator clock cyclesMemory: 1 +ea program words
Page 3 and 4:
DSP56K FAMILY INTRODUCTIONDSP56K CE
Page 5:
Motorola reserves the right to make
Page 8 and 9:
Table of Contents (Continued)Paragr
Page 10 and 11:
ParagraphNumberTable of Contents (C
Page 13 and 14:
FigureNumberList of Figures (Contin
Page 15:
List of Tables (Continued)TablePage
Page 19 and 20:
1.1 INTRODUCTIONThe DSP56K family i
Page 21 and 22:
Fewer componentsStable, determinist
Page 23 and 24:
Digital FilteringFinite Impulse Res
Page 25 and 26:
architecture matches the shape of t
Page 27 and 28:
• DSP56001 Compatibility - All me
Page 29:
SECTION 2DSP56K CENTRAL ARCHITECTUR
Page 32 and 33:
--I«a:w:ca.ffi~a. a.24-Bit 56KModu
Page 34 and 35:
-rectly addressable registers: the
Page 37 and 38:
3.1 DATA ARITHMETIC LOGIC UNITThis
Page 39 and 40:
3.2.1 Data ALU Input Registers (X1,
Page 41 and 42:
"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
Page 43 and 44:
3.2.4 Accumulator ShifterThe accumu
Page 45 and 46:
Table 3-1 Limited Data ValuesDestin
Page 47 and 48:
_--- N BITS ---_TWOS COMPLEMENT INT
Page 49 and 50:
CASE I: IF AO < $800000 (1/2), THEN
Page 51 and 52:
one instruction cycle. The ANDI ins
Page 53:
3.5 DATA ALU PROGRAMMING MODELThe D
Page 57 and 58:
4.1 ADDRESS GENERATION UNIT AND ADD
Page 59 and 60:
!---LOWADDRESS ALU -----I~.j.I.....
Page 61 and 62:
•••••••• _ ........
Page 63 and 64:
4.4.1 Address Register Indirect Mod
Page 65 and 66:
EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
Page 67 and 68:
EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
Page 69 and 70:
EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
Page 71 and 72:
Table 4-2 Address Modifier SummaryM
Page 73 and 74:
ADDRESS -f-_POINTERUPPER BOUNDARYiM
Page 75 and 76:
EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
Page 77 and 78:
oundary gives a 16-bit binary numbe
Page 79 and 80:
4.4.2.4 Address-Modifier-Type Encod
Page 81:
SECTION 5PROGRAM CONTROL UNIT-
Page 84 and 85:
X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
Page 86 and 87:
interruptible since they are fetche
Page 88 and 89:
PROGRAM CONTROL UNIT-23 1615 023 16
Page 90 and 91:
The GGR is a special purpose contro
Page 92 and 93:
If S 1 =0 and SO=O (no scaling)then
Page 94 and 95:
-23 876543210I * 1* JSO I * I Mel y
Page 96 and 97:
5.4.5.1 Stack Pointer (Bits 0-3)The
Page 98 and 99:
-DATA ARITHMETIC LOGIC UNITINPUT RE
Page 101 and 102:
6.1 INSTRUCTION SET INTRODUCTIONThe
Page 103 and 104:
shown in Figure 6-2. Most instructi
Page 105 and 106:
23 87 0L...-I ___-'-I_---'I BUS~ LS
Page 107 and 108:
The MR and CCR may be accessed indi
Page 109 and 110:
6.3.4 Operand ReferencesThe DSP sep
Page 111 and 112:
Some address register indirect mode
Page 113 and 114:
EXAMPLE A: IMMEDIATE INTO 24-BIT RE
Page 115 and 116:
EXAMPLE A: IMMEDIATE SHORT INTO AO,
Page 117 and 118:
EXAMPLE A: MOVE P: $3200,XOBEFORE E
Page 119 and 120:
Table 6-1 Addressing Modes SummaryA
Page 121 and 122:
6.4.2 LogicallnstructlonsThe logica
Page 123 and 124:
START OF LOOP1)SP+ 1 • SP; LA. SS
Page 125 and 126:
OPCODE/OPERANDSPARALLEL MOVE EXAMPL
Page 127:
SECTION 7PROCESSING STATES-
Page 130 and 131:
Each instruction requires a minimum
Page 132 and 133:
second instruction of the downloade
Page 134 and 135:
The DO instruction is another instr
Page 136 and 137:
SP and SSH/SSL register manipulatio
Page 138 and 139:
7.3.1 Interrupt TypesThe DSP56K rel
Page 140 and 141:
Table 7-2 Status Register Interrupt
Page 142 and 143:
7.3.3 Interrupt SourcesInterrupts c
Page 144 and 145:
interrupts makes it very useful for
Page 146 and 147:
MAINPROGRAMFETCHESLONG INTERRUPTSER
Page 148 and 149:
7.3.3.3 Other Interrupt SourcesOthe
Page 150 and 151:
7.3.4 Interrupt ArbitrationInterrup
Page 152 and 153:
7.3.7 Interrupt Instruction Executi
Page 154 and 155:
MAINPROGRAMMEMORYINTERRUPT SYNCHRON
Page 156 and 157:
MAINPROGRAMFETCHESINTERRUPTSYNCHRON
Page 158 and 159:
MAINPROGRAMFAST INTERRUPTVECTORLONG
Page 160 and 161:
MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
Page 162 and 163:
7.5 WAIT PROCESSING STATEThe WAIT i
Page 164 and 165:
The stop processing state halts all
Page 166 and 167:
the first instruction fetch). If th
Page 168:
RESET -----------------------------
Page 172 and 173:
16 - BIT INTERNALADDRESS BUSESX ADD
Page 174 and 175:
8.2.2.1 Address (AO-A15)These three
Page 177:
SECTION 9PLL CLOCK OSCILLATOR-
Page 180 and 181:
X MEMORYRAM/ROMEXPANSION24-Bit56KMo
Page 182 and 183:
23 22 21 20 19 18 17 16 15 14 13 12
Page 184 and 185:
cleared. To enable rapid recovery w
Page 186 and 187:
-CLVCCVCC for the CKOUT output. The
Page 188 and 189:
4. For all input frequencies which
Page 190 and 191:
While the PLL is regaining lock, th
Page 193 and 194:
10.1 ON-CHIP EMULATION INTRODUCTION
Page 195 and 196:
10.2.2 Debug Serial Clock/Chip Stat
Page 197 and 198:
76543210I R/W I GO I EX I RS41 RS31
Page 199 and 200:
shifted in (so a new command is ava
Page 201 and 202:
10.3.4.4 Software Debug Occurrence
Page 203 and 204:
10.4.4 Memory High Address Comparat
Page 205 and 206:
10.6.1 External Debug Request Durin
Page 207 and 208:
PABCIRCULARBUFFERPOINTERDSCKDSOFigu
Page 209 and 210:
are serially available to the exter
Page 211 and 212:
k. ACKI. ClKm. Send command READ FI
Page 213 and 214:
19. ACK20. Send command READ GDB RE
Page 215 and 216:
10.11.6.1 Case 1: Return To The Pre
Page 217:
SECTION 11ADDITIONAL SUPPORTDr. BuB
Page 220 and 221:
The following is a partial list of
Page 222 and 223:
• In-line assembler language code
Page 224 and 225:
I Document 10 I Version Synopsis I
Page 226 and 227:
Page 228 and 229:
I Document ID I Version Synopsis I
Page 230 and 231:
Page 232 and 233:
11.5 MOTOROLA DSP NEWSThe Motorola
Page 234 and 235:
DIGITAL SIGNAL PROCESSINGAlan V. Op
Page 236 and 237:
C Programming Language:Controls:. C
Page 238 and 239:
Image Processing:DIGITAL IMAGE PROC
Page 240 and 241:
LINEAR PREDICTION OF SPEECHJ. D. Ma
Page 243 and 244:
A.1 APPENDIX A INTRODUCTIONThis app
Page 245 and 246:
XnYnTable A-1 Instruction Descripti
Page 247 and 248:
Table A-1 Instruction Description N
Page 249 and 250: Table A-1 Instruction Description N
Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
Page 253 and 254: The address register indirect addre
Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
Page 257 and 258: S1 SO Scaling Mode Signed Integer P
Page 259 and 260: Table A-5 Condition Code Computatio
Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
Page 263 and 264: ABSAbsolute ValueABSInstruction For
Page 265 and 266: ADC Add Long with Carry ADCresult.
Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
Page 269 and 270: ADDL Shift Left and Add Accumulator
Page 271 and 272: ADDR Shift Right and Add Accumulato
Page 273 and 274: ANDLogical ANDANDInstruction Format
Page 275 and 276: ANDIAND Immediate with Control Regi
Page 277 and 278: ASL Arithmetic Shift Accumulator Le
Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
Page 281 and 282: BCHG Bit Test and Change BCHGExplan
Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
Page 291 and 292: BClRBit Test and ClearBClRInstructi
Page 293 and 294: BClRBit Test and ClearBClRInstructi
Page 295 and 296: BClR Bit Test and Clear BClRNotes:
Page 297 and 298: BSET Bit Test and Set BSETExplanati
Page 299: BSETBit Test and SetBSETInstruction
Page 303 and 304: BSET Bit Test and Set BSETNotes: If
Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
Page 311 and 312: CLRClear AccumulatorCLRInstruction
Page 313 and 314: CMP Compare CMPCondition Codes:15 1
Page 315 and 316: CMPM Compare Magnitude CMPMConditio
Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
Page 321 and 322: DEC Decrement by One DECInstruction
Page 323 and 324: DIV Divide Interation DIVThe DIV in
Page 325 and 326: DIV Divide Interation DIVNote that
Page 327 and 328: DIVInstruction Format:DIV S,DDivide
Page 329 and 330: DO Start Hardware Loop DOexecuted 6
Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
Page 333 and 334: DOStart Hardware LoopDOInstruction
Page 335 and 336: DOStart Hardware LoopDOInstruction
Page 337 and 338: DO Start Hardware Loop DONotes: If
Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
Page 341 and 342: EOR Logical Exclusive OR EORInstruc
Page 343 and 344: ILLEGALIllegal Instruction Interrup
Page 345 and 346: INC Increment by One INCInstruction
Page 347 and 348: Jcc Jump Conditionally JccRestricti
Page 349 and 350: JccJump ConditionallyJccEffectiveAd
Page 351 and 352:
JCLR Jump If Bit Clear JCLRRestrict
Page 353 and 354:
JCLRJump If Bit ClearJCLRInstructio
Page 355 and 356:
JCLR Jump If Bit Clear JCLRInstruct
Page 357 and 358:
JMPJumpJMPInstruction Fields:xxx=12
Page 359 and 360:
JSccJump to Subroutine Conditionall
Page 361 and 362:
JScc Jump to Subroutine Conditional
Page 363 and 364:
JSCLR Jump to Subroutine if Bit Cle
Page 365 and 366:
JSCLRJump to Subroutine If Bit Clea
Page 367 and 368:
JSCLRJump to Subroutine If Bit Clea
Page 369 and 370:
JSCLR Jump to Subroutine If Bit Cle
Page 371 and 372:
JSET Jump if Bit Set JSETRestrictio
Page 373 and 374:
JSETJump if Bit SetJSETInstruction
Page 375 and 376:
JSET Jump If Bit Set JSETInstructio
Page 377 and 378:
JSR Jump to Subroutine JSRInstructi
Page 379 and 380:
JSSET Jump to Subroutine if Bit Set
Page 381 and 382:
JSSETJump to Subroutine if Bit SetJ
Page 383 and 384:
JSSET Jump to Subroutine if Bit Set
Page 385 and 386:
LSL Logical Shift Left LSLCondition
Page 387 and 388:
LSR Logical Shift Right LSRConditio
Page 389 and 390:
LUALoad Updated AddressLUACondition
Page 391 and 392:
MAC Signed Multiply-Accumulate MACC
Page 393 and 394:
MACSigned Multiply-AccumulateMACTim
Page 395 and 396:
MACR Signed Multiply-Accumulate and
Page 397 and 398:
MACR Signed MUltiply-Accumulate and
Page 399 and 400:
MOVE Move Data MOVEExplanation of E
Page 401 and 402:
MOVE Move Data MOVEWhen a 56-bit ac
Page 403 and 404:
No Parallel Data MoveInstruction Fo
Page 405 and 406:
I Immediate Short Data Move IExampl
Page 407 and 408:
I Immediate Short Data Move IDDD d
Page 409 and 410:
R Register to Register Data Move RE
Page 411 and 412:
R Register to Register Data Move RI
Page 413 and 414:
uAddress Register UpdateuInstructio
Page 415 and 416:
X: X Memory Data Move X:Note:Due to
Page 417 and 418:
X: X Memory Data Move X:S D DS,D d
Page 419 and 420:
X: X Memory Data Move X:S D DS,D d
Page 421 and 422:
X:R X Memory and Register Data Move
Page 423 and 424:
Page 425 and 426:
Page 427 and 428:
Y: Y Memory Data Move Y:Note: This
Page 429 and 430:
Y: Y Memory Data Move Y:S D DS,D d
Page 431 and 432:
Y: Y Memory Data Move Y:S D DS,D d
Page 433 and 434:
R:V Register and V Memory Data Move
Page 435 and 436:
R:V Register and Y Memory Data Move
Page 437 and 438:
R:V Register and Y Memory Data Move
Page 439 and 440:
L: Long Memory Data Move L:Example:
Page 441 and 442:
L: Long Memory Data Move L:Instruct
Page 443 and 444:
X: Y: xv Memory Data Move X: Y:Exam
Page 445 and 446:
X: Y: xv Memory Data Move X: Y:S1 D
Page 447 and 448:
MOVEC Move Control Register MOVECst
Page 449 and 450:
MOVEC Move Control Register MOVECCo
Page 451 and 452:
MOVECMove Control RegisterMOVECInst
Page 453 and 454:
MOVEC Move Control Register MOVECTi
Page 455 and 456:
MOVEM Move Program Memory MOVEMoper
Page 457 and 458:
MOVEM Move Program Memory MOVEMInst
Page 459 and 460:
MOVEMMove Program MemoryMOVEMInstru
Page 461 and 462:
MOVEP Move Peripheral Data MOVEPist
Page 463 and 464:
MOVEP Move Peripheral Data MOVEPCon
Page 465 and 466:
MOVEP Move Peripheral Data MOVEPIns
Page 467 and 468:
MOVEP Move Peripheral Data MOVEPIns
Page 469 and 470:
MPY Signed Multiply MPYExplanation
Page 471 and 472:
MPY Signed Multiply MPYInstruction
Page 473 and 474:
MPYR Signed Multiply and Round MPYR
Page 475 and 476:
MPYR Signed Multiply and Round MPYR
Page 477 and 478:
NEGNegate AccumulatorNEGInstruction
Page 479 and 480:
NOPNo OperationNOPInstruction Forma
Page 481 and 482:
NORM Normalize Accumulator Iteratio
Page 483 and 484:
NOTLogical ComplementNOTInstruction
Page 485 and 486:
ORLogical Inclusive ORORInstruction
Page 487 and 488:
ORI OR Immediate with Control Regis
Page 489 and 490:
REP Repeat Next Instruction REPRest
Page 491 and 492:
REPRepeat Next InstructionREPInstru
Page 493 and 494:
REPRepeat Next InstructionREPInstru
Page 495 and 496:
REP Repeat Next Instruction REPNote
Page 497 and 498:
RESETReset On-Chip Peripheral Devic
Page 499 and 500:
RND Round Accumulator RNDConvergent
Page 501 and 502:
RNDRound AccumulatorRNDInstruction
Page 503 and 504:
ROL Rotate Left ROLCondition Codes:
Page 505 and 506:
ROR Rotate Right RORCondition Codes
Page 507 and 508:
RTIReturn from InterruptRTIConditio
Page 509 and 510:
RTSReturn from SubroutineRTSInstruc
Page 511 and 512:
sec Subtract Long with Carry secExp
Page 513 and 514:
secSubtract Long with CarrysecInstr
Page 515 and 516:
STOPStop Instruction ProcessingSTOP
Page 517 and 518:
SUB Subtract SUBCondition Codes:S -
Page 519 and 520:
SUBL Shift Left and Subtract Accumu
Page 521 and 522:
SUBR Shift Right and Subtract Accum
Page 523 and 524:
SWISoftware InterruptSWICondition C
Page 525 and 526:
Tee Transfer Conditionally Teetion
Page 527 and 528:
Tee Transfer Conditionally TeeInstr
Page 529 and 530:
TFR Transfer Data ALU Register TFRC
Page 531 and 532:
TSTTest AccumulatorTSTInstruction F
Page 533 and 534:
WAIT Wait for Interrupt WAITConditi
Page 535 and 536:
including the number of words per i
Page 537 and 538:
5. Compute final results.Thus, base
Page 539 and 540:
JLC (R2+N2)will requireand will exe
Page 541 and 542:
Table A-6 Instruction Timing Summar
Page 543 and 544:
Note that the "ap" term in Table A-
Page 545 and 546:
Table A-14 Memory Access Timing Sum
Page 547 and 548:
Other RestrictionsDO SSH,xxxxJSR to
Page 549 and 550:
Immediately before MOVEC from SSH o
Page 551 and 552:
A.9.S REP RestrictionsThe REP instr
Page 553 and 554:
Table A-18 Triple-Bit Register Enco
Page 555 and 556:
Table A-24 Program Control Unit Reg
Page 557 and 558:
R: Register to Register Parallel Da
Page 559 and 560:
JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
Page 561 and 562:
JSSET#n,S,xxxx23 16 15 87 000001011
Page 563 and 564:
BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
Page 565 and 566:
MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
Page 567 and 568:
LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
Page 569 and 570:
ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
Page 571 and 572:
Table A-28 Operation Code QQQ Decod
Page 573 and 574:
Table A-30 Special Case #10 P E R C
Page 575 and 576:
NEGD23 87 43 0DATA BUS MOVE FIELDLS
Page 577:
ADDRS,D23 87 43 oDATA BUS MOVE FIEL
Page 580 and 581:
lEI
Page 582 and 583:
Table 8-1 27-MHz Benchmark Results
Page 584 and 585:
.*._---*-----*-------**-------....
Page 586 and 587:
;Latest Revision - September 30, 19
Page 588 and 589:
All coefficients are divided by 2:w
Page 590 and 591:
Real input FFT based on Glenn Bergl
Page 592 and 593:
countountcountcountorg y:coefset 0d
Page 594 and 595:
; Real-Valued FFT for MOTOROLA DSP5
Page 596 and 597:
; first group in the last passmove
Page 599 and 600:
A Accumulator ....... ' ...........
Page 601 and 602:
-H- fast ..........................
Page 603 and 604:
PGND ..............................
Page 605 and 606:
DSP56K FAMILY INTRODUCTIONDSP56K CE
show all

section 7 - Index of

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?