section 7 - Index of

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DSP56K FAMILY INTRODUCTIONDSP56K CENTRAL ARCHITECTURE OVERVIEWDATA ARITHMETIC LOGIC UNITADDRESS GENERATION UNITPROGRAM CONTROL UNITINSTRUCTION SET INTRODUCTIONPROCESSING STATESPORTAPLL CLOCK OSCILLATORON-CHIP EMULATION (OnCE)ADDITIONAL SUPPORTINSTRUCTION SET DETAILSBENCHMARK PROGRAMSINDEX
Page 4 and 5: DSP56K FAMILY INTRODUCTION_DSP56K C
Page 7 and 8: TABLE OF CONTENTSParagraphNumberTit
Page 9 and 10: Table of Contents (Continued)Paragr
Page 11: LIST of FIGURESFigureNumberTitlePag
Page 14 and 15: LIST of TABLESTableNumberTitle1-1 B
Page 17: SECTION 1DSP56K FAMILY INTRODUCTION
Page 20 and 21: ANALOG FILTERR fC fX(tlbX(t)INPUTFR
Page 22 and 23: The DSP56K family is not designed f
Page 24 and 25: Image ProcessingPattern Recognition
Page 26 and 27: • Precision - The data paths are
Page 28 and 29: Section 7 - Processing StatesThis s
Page 31 and 32: 2.1 DSP56K CENTRAL ARCHITECTURE OVE
Page 33 and 34: three-input multiplexer that can se
Page 35: SECTION 3DATA ARITHMETIC LOGIC UNIT
Page 38 and 39: X MEMORYRAM/ROMEXPANSION24 Bit56KMo
Page 40 and 41: egister contents. The registers may
Page 42 and 43: Accumulator ADATA ALU ACCUMULATOR R
Page 44 and 45: WITHOUT L1MITING*WITH L1MITING*~ 0
Page 46 and 47: tors allow word growth so that the
Page 48 and 49: SIGNED MULTIPLICATION N x N .2N - 1
Page 50 and 51: 3.4 DOUBLE PRECISION MULTIPLY MODET
Page 52 and 53:
cision values and accumulated using
Page 55:
-SECTION 4ADDRESS GENERATION UNIT
Page 58 and 59:
X MEMORYRAM/ROMEXPANSION24-Bit 56KM
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esult of the first full adder to a
Page 62 and 63:
Table 4-1 Address Register Indirect
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EXAMPLE: MOVE A1,X: (RO)BEFORE EXEC
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EXAMPLE: MOVE VO,V: (R3)-BEFORE EXE
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EXAMPLE: MOVE X:(R4)-N4,AOBEFORE EX
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EXAMPLE: MOVE X: -(R5),B1BEFORE EXE
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4.4.2.2 Modulo ModifierWhen the val
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(Rn) ± Nn MOD MWHERE Nn = 2k (Le.,
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The Mn register is loaded with the
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The term bit reverse with respect t
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LINEAR ADDRESS MODIFIERMO = 255 = 1
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5.1 PROGRAM CONTROL UNITThis sectio
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The program control unit implements
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EXAMPLE pROGRAM SEGMENTInstruction
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MRCCR15 14 13 12 11 10 9 8 7 6 5 4
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5.4.2.6 Extension (Bit 5)The extens
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The scaling mode affects data read
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the SS. Since each SS location can
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5.4.5.4 Reserved Stack Pointer Regi
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SECTION 6INSTRUCTION SET INTRODUCTI
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-47~3XlXIa 23XO55I I A223 8755I I 6
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7 0c:=J BYTE15 0IISHORT WORD23 0II
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23 87 0I I I BUS'----v---JMR, GGR,
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AddressALURnNnMnAddress Registers R
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6.3.4.4.2 V Memory ReferencesThe op
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6.3.5.3 Special Addressing ModesThe
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EXAMPLE: MOVE Y:$5432,BOBEFORE EXEC
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EXAMPLE: JMP $123BEFORE EXECUTIONP
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EXAMPLE: MOVEPA1, X:«$FFFEBEFORE E
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6.4.1 Arithmetic InstructionsThe ar
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6.4.3 Bit Manipulation Instructions
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DODO~n1,END1#n2,END2[MOVE;END2 ADD
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-JCLRJSETJSccJSRJSCLRJSSETNOPREPRES
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7.1 PROCESSING STATESThe DSP56K pro
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Case 2: One of the more common sequ
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Note 1: INST 3 may be executed at t
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The restricted instructions at LA-2
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the main uses of interrupts is to t
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$0100MAINPROGRAMFAST INTERRUPT SERV
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Table 7-3 Interrupt Priority Level
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automatically when they are service
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MAINPROGRAMFETCHESFAST INTERRUPTSER
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ILLEGAL INSTRUCTION INTERRUPTRECOGN
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MAINPROGRAMFETCHESTRACE INSTRUCTION
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7.3.6 . Instructions Preceding the
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MAINPROGRAMMEMORYIINTERRUPT SYNCHRO
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6. The fast interrupt returns witho
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MAINPROGRAMFAST INTERRUPTVECTORLONG
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mented to one (see Figure 7-13). Du
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MAINPROGRAMFETCHES~~I~-lI~~INTEARlP
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INTERRUPT CONTROL CYCLE 1rINTERRUPT
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IRQA ---------------.,FETCH n3 n4 -
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the period of the first oscillator
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8.1 PORT A OVERVIEWPort A provides
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e subdivided into three additional
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WT) facility, which allows an exter
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9.1 PLL CLOCK OSCILLATOR INTRODUCTI
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The charge pump loop filter receive
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shows the programming of the DFO-DF
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Table 9-4 Clock Output Disable Bits
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9.4 PLL OPERATION CONSIDERATIONSThe
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chip clock. (Here, T3 is equal to t
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SECTION 10ON-CHIP EMULATION (OnCE)-
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...I~W:I:0...ffi~0...0...24-BitS6KM
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10.2.4 Debug Request Input (DR)The
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10.3.1.2 Exit Command (EX) Bit 5If
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When BC3-BCO=0011, program memory b
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OSCKPAB XAB YABOSO OSI~-- MEMORY BU
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To initiate the trace mode of opera
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the trace counter is decremented af
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the external command controller whe
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The external command controller act
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-After 24 bits have been received t
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10.11.4 Executing a Single-Word DSP
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PDS contains the second word of the
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11.1 USER SUPPORTUser support from
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the DSP56K family of processors•
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11.3.3 Support Integrated Circuits:
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I Document ID I Version Synopsis I
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Page 229 and 230:
Page 231 and 232:
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11.12 TRAINING COURSES - (602) 897-
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ADAPTIVE SIGNAL PROCESSINGB. Widrow
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Graphics:CGM AND CGID. B. Arnold an
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NUMERICAL RECIPES IN C - THE ART OF
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APPENDIX AINSTRUCTION SET DETAILSAr
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word is optional, it is so indicate
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Table A-1 Instruction Description N
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Table A-1 Instruction Description N
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A.4 ADDRESSING MODESThe addressing
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Addressing ModeTable A-3 DSP56K Add
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Table A-4 Addressing Mode Modifier
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S (Scaling Bit)The scaling bit (S)
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C (Carry Bit)Set if a carry is gene
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The following notes apply to Table
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ABS Absolute Value ABSOperation:I D
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ACC Add Long with Carry ACCOperatio
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ADD Add ADDOperation:S+D-+D (parall
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ADDL Shift Left and Add Accumulator
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ADDR Shift Right and Add Accumulato
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AND Logical AND ANDOperation:S - 0[
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ANDIAND Immediate with Control Regi
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ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGOperat
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BCHGBit Test and ChangeBCHGFor othe
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and Ch~ngeBCHGInstruct
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BCLR Bit Test and Clear BCLROperati
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BCLRBit Test and ClearBCLRFor other
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BCLRBit Test and ClearBCLRInstructi
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BCLRBit Test and ClearBCLRInstructi
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BSET Bit Test and Set BSElOperation
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BSElBit Test and SetBSElFor other d
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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8TST Bit Test 8TSTOperation:Assembl
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BTSTBit TestBTSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLR Clear Accumulator CLROperation:
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CMP Compare CMPOperation:Assembler
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CMPM Compare Magnitude CMPMOperatio
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DEBUG Enter Debug Mode DEB,UGOperat
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DEBUGcc Enter Debug Mode Conditiona
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DECDecrement by OneDECOperation:0-1
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DIV Divide Interation DIVOperation:
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DIV Divide Interation DIVExample: (
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DIV Divide Interatlon DIVA complete
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DOStart Hardware LoopDOOperation:As
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DO Start Hardware Loop DOmented by
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DOStart Hardware LoopDOExample:DO #
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DO Start Hardware Loop DOInstructio
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DO Start Hardware Loop DOInstructio
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ENDDO End Current DO Loop ENDDOOper
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EOR Logical Exclusive OR EOROperati
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ILLEGALIllegal Instruction Interrup
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INC Increment by One INCOperation:A
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JccJump ConditionallyJccOperation:I
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Jcc Jump Conditionally JccInstructi
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JCLR Jump If Bit Clear JCLROperatio
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JCLRJump if Bit ClearJCLRInstructio
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JCLRJump if Bit ClearJCLRInstructio
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JMPJumpJMPOperation:Oxxx --t PCea -
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JScc Jump to Subroutine Conditional
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine If Bit Cle
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine if Bit Clea
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JSCLR Jump to Subroutine if Bit Cle
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JSETJump If Bit SetJSETOperation:If
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JSETJump If Bit SetJSETInstruction
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JSETJump if Bit SetJSETInstruction
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JSR Jump to Subroutine JSROperation
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JSSET Jump to Subroutine if Bit Set
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JSSETJump to Subroutine If Bit SetJ
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JSSETJump to Subroutine If Bit SetJ
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LSL Logical ~hlft Left LSLOperation
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LSR Logical Shift Right LSROperatio
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LUALoad Updated AddressLUAOperation
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MAC Signed Multiply-Accumulate MACO
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed Multiply-Accumulate and
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MOVE Move Data MOVEOperation:S~DAss
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MOVE Move Data MOVEParallel Move De
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No Parallel Data MoveOperation:Asse
Page 404 and 405:
IImmediate Short Data MoveIOperatio
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IImmediate Short Data MoveIConditio
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RRegister to Register Data MoveROpe
Page 410 and 411:
R Register to Register Data Move RC
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uAddress Register UpdateuOperation:
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X: X Memory Data Move X:Operation:A
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X: X Memory Data Move X:Instruction
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X: X Memory Data MoveX:Instruction
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X:RX Memory and Register Data MoveX
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X:R X Memory and Register Data Move
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X:R X Memory and Register Data Move
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Y: V Memory Data Move Y:Operation:A
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V: Y Memory Data Move V:Note: The M
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V: Y Memory Data MoveV:Instruction
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R:V Register and V Memory Data Move
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R:Y Register and Y Memory Data Move
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R:VRegister and V Memory Oata MoveR
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L: Long Memory Data Move L:Operatio
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L: Long Memory Data Move L:Instruct
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X: V: xv Memory Data Move X: V:Oper
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X: V: xv Memory Data Move X: V:Note
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MOVEC Move Control Register MOVECOp
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MOVEC Move Control Register MOVECA
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MOVECMove Control RegisterMOVECRegi
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MOVECMove Control RegisterMOVECInst
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MOVEMMove Program MemoryMOVEMOperat
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MOVEM Move Program Memory MOVEMExam
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MOVEM Move Program Memory MOVEMS D
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MOVEP Move Peripheral Data MOVEPOpe
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_______-----'MOVEP Move Peripheral
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MOVEPMove Peripheral DataMOVEPInstr
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MOVEPMove Peripheral DataMOVEPInstr
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MPY Signed Multiply MPYOperation:±
Page 470 and 471:
MPY Signed Multiply MPYInstruction
Page 472 and 473:
MPYR Signed Multiply and Round MPYR
Page 474 and 475:
MPYR Signed Multiply and Round MPYR
Page 476 and 477:
NEG Negate Accumulator NEGOperation
Page 478 and 479:
NOP No Operation NOPOperation:PC+1-
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NORM Normalize Accumulator Iteratio
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NOT Logical Complement NOTOperation
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OR Logical Inclusive OR OROperation
Page 486 and 487:
ORI OR Immediate with Control Regis
Page 488 and 489:
REP Repeat Next Instruction REPOper
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REP Repeat Next Instruction REPExpl
Page 492 and 493:
REPRepeat Next InstructionREPInstru
Page 494 and 495:
REP Repeat Next Instruction REPInst
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RESETReset On-Chip Peripheral Devic
Page 498 and 499:
RND Round Accumulator RNDOperation:
Page 500 and 501:
RND Round Accumulator RNDCondition
Page 502 and 503:
ROL Rotate Left ROLOperation:r47 24
Page 504 and 505:
ROR Rotate Right ROROperation: c:c~
Page 506 and 507:
RTI Return from Interrupt RTIOperat
Page 508 and 509:
RTS Return from Subroutine RTSOpera
Page 510 and 511:
SBC Subtract Long with Carry secOpe
Page 512 and 513:
SBC Subtract Long with Carry SBCCon
Page 514 and 515:
STOP Stop Instruction Processing ST
Page 516 and 517:
SUB Subtract SUBOperation:O-S -4 D
Page 518 and 519:
SUBL Shift Left and Subtract Accumu
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SUBR Shift Right and Subtract Accum
Page 522 and 523:
SWI Software Interrupt SWIOperation
Page 524 and 525:
Tee Transfer Conditionally TeeOpera
Page 526 and 527:
Tee Transfer Conditionally TeeInstr
Page 528 and 529:
TFR Transfer Data ALU Register TFRO
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TST Test Accumulator TSTOperation:A
Page 532 and 533:
WAIT Wait for Interrupt WAITOperati
Page 534 and 535:
A.a INSTRUCTION TIMINGThis section
Page 536 and 537:
cycles that may be required over an
Page 538 and 539:
additional (if any) instruction pro
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3. Evaluate the "ap" term using Tab
Page 542 and 543:
Table A-7 Parallel Data Move Timing
Page 544 and 545:
Table A-12 RTIIRTS Timing SummaryOp
Page 546 and 547:
A.9.1 Restrictions Near the End of
Page 548 and 549:
Immediately before ENDDOBCHG lA, lC
Page 550 and 551:
Immediately before JSCLR from SSH o
Page 552 and 553:
Section A.10.4 gives the encoding f
Page 554 and 555:
Table A-20 Five-Bit Register Encodi
Page 556 and 557:
A.10.2 Instruction Encoding for the
Page 558 and 559:
A.10.3 Instruction Encoding for Ins
Page 560 and 561:
JSETJSET#n,X:ea,xxxx#n,Y:ea,xxxx23
Page 562 and 563:
BCLRBCLR#n,X:pp#n,Y:pp23I 0 0 0 016
Page 564 and 565:
BCLR23#n,O0 0 0 0 1 016 15 871 o \
Page 566 and 567:
DODOX:ea,exprV:ea,expr23 16 15 87 0
Page 568 and 569:
MPYR (±)S,#n,DDEBUGccDEBUG23 16 15
Page 570 and 571:
ILLEGALRTINOP23 16 15 87 0I 0 0 0 0
Page 572 and 573:
Nonmultlply Instruction EncodingThe
Page 574 and 575:
EORS,D23 87 43 0DATA BUS MOVE FIELD
Page 576 and 577:
NOTD23 87 43 0DATA BUS MOVE FIELDSU
Page 579 and 580:
APPENDIX BBENCHMARK PROGRAMS-
Page 581 and 582:
B.1 INTRODUCTIONTable 8-1 provides
Page 583 and 584:
page 132,66,0,6opt rc.*************
Page 585 and 586:
;This program originally available
Page 587 and 588:
page 132,66,0,6opt rc...._..__.....
Page 589 and 590:
page 132,60,1,1;newlms2n.asm; New I
Page 591 and 592:
,; Main program to call the rfft-56
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jle -'oopmove xO,rOmove y1,amove x:
Page 595 and 596:
FirstGrouplnPassdo nO,FirstGrouplnP
Page 597:
; Real input data are split into tw
Page 600 and 601:
zero (bit 2) .................... 5
Page 602 and 603:
-M- OnCE Commands .................
Page 604 and 605:
Saturation Arithmetic .............
Page 606:
DSP56K FAMILY INTRODUCTION_DSP56K C
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