section 7 - Index of
section 7 - Index of section 7 - Index of
BSET Bit Test and Set BSElOperation:Assembler Syntax:D[n] ~ C; BSET #n,X:ea1 ~ D[n]D[n] ~ C; BSET #n,X:aa1 ~ D[n]D[n] ~ C; BSET #n,X:pp1 ~ D[n]D[n] ~ C; BSET #n,Y:ea1 ~ D[n]D[n] ~ C; BSET #n,Y:aa1 ~ D[n]D[n] ~ C; BSET #n,Y:pp1 ~ D[n]D[n] ~ C; BSET #n,D1 ~ D[n]Description: Test the nth bit of the destination operand 0, set it, and store the result inthe destination location. The state of the nth bit is stored in the carry bit C of the conditioncode register. The bit to be tested is selected by an immediate bit number from 0-23.This instruction performs a read-modify-write operation on the destination location usingtwo destination accesses before releasing the bus. This instruction provides a test-andsetcapability which is useful for synchronizing multiple processors using a shared memory.This instruction can use all memory alterable addressing modes.Example:BSET #$0,X:«$FFE5 ;test and clear bit 14 in liD Port B Data Reg.X:$FFE5 1 '--____Before Execution$ 0_00_0_0 o __ -.l X:$FFE5 1L--__After Execution--'-$°_°°_°°_1__--'SRI '--____ $0_3_00 __-.l SRI'--____ ~$_03_0_0 __ ~
BSET Bit Test and Set BSETExplanation of Example: Prior to execution, the 24-bit X location X:$FFE5 (liD port Cdata register) contains the value $000000. The execution of the BSET #$0,X:«$FFE5instruction tests the state of the oth bit in X:$FFE5, sets the carry bit C accordingly, andthen sets the Oth bit in X:$FFE5.Condition Codes:I"F I OM I T I" I SI I SO I 1115 14 13 12 11 10 9 8 7 6 5 4 3 2I 10 I s I l... MR • C CCR1 0CCR Condition Codes:For destination operand SR:C- Set if bit 0 is specified. Not affected otherwise.V - Set if bit 1 is specified. Not affected otherwise.Z - Set if bit 2 Is specified. Not affected otherwise.N - Set if bit 3 is specified. Not affected otherwise.U - Set if bit 4 is specified. Not affected otherwise.E - Set if bit 5 Is specified. Not affected otherwise.L - Set if bit 6 is specified. Not affected otherwise.S - Set If bit 7 Is specified. Not affected othelWise.For destination operand A or B:S -Computed according to the definition. See Notes on page A-63.L - Set if data limiting has occurred. See Notes on page A-63.E - Not affectedU - Not affectedN - Not affectedZ - Not affectedV - Not affectedC - Set if bit tested Is set. Cleared othelWise.
- Page 245 and 246: XnYnTable A-1 Instruction Descripti
- Page 247 and 248: Table A-1 Instruction Description N
- Page 249 and 250: Table A-1 Instruction Description N
- Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
- Page 253 and 254: The address register indirect addre
- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
- Page 259 and 260: Table A-5 Condition Code Computatio
- Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
- Page 263 and 264: ABSAbsolute ValueABSInstruction For
- Page 265 and 266: ADC Add Long with Carry ADCresult.
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295: BClR Bit Test and Clear BClRNotes:
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
- Page 325 and 326: DIV Divide Interation DIVNote that
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
- Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
- Page 341 and 342: EOR Logical Exclusive OR EORInstruc
- Page 343 and 344: ILLEGALIllegal Instruction Interrup
- Page 345 and 346: INC Increment by One INCInstruction
BSET Bit Test and Set BSElOperation:Assembler Syntax:D[n] ~ C; BSET #n,X:ea1 ~ D[n]D[n] ~ C; BSET #n,X:aa1 ~ D[n]D[n] ~ C; BSET #n,X:pp1 ~ D[n]D[n] ~ C; BSET #n,Y:ea1 ~ D[n]D[n] ~ C; BSET #n,Y:aa1 ~ D[n]D[n] ~ C; BSET #n,Y:pp1 ~ D[n]D[n] ~ C; BSET #n,D1 ~ D[n]Description: Test the nth bit <strong>of</strong> the destination operand 0, set it, and store the result inthe destination location. The state <strong>of</strong> the nth bit is stored in the carry bit C <strong>of</strong> the conditioncode register. The bit to be tested is selected by an immediate bit number from 0-23.This instruction performs a read-modify-write operation on the destination location usingtwo destination accesses before releasing the bus. This instruction provides a test-andsetcapability which is useful for synchronizing multiple processors using a shared memory.This instruction can use all memory alterable addressing modes.Example:BSET #$0,X:«$FFE5 ;test and clear bit 14 in liD Port B Data Reg.X:$FFE5 1 '--____Before Execution$ 0_00_0_0 o __ -.l X:$FFE5 1L--__After Execution--'-$°_°°_°°_1__--'SRI '--____ $0_3_00 __-.l SRI'--____ ~$_03_0_0 __ ~
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