section 7 - Index of
section 7 - Index of section 7 - Index of
BCLRBit Test and ClearBCLRFor other destination operands:C - Set If bit tested is set. Cleared otherwise.V - Not affectedZ - Not affectedN - Not affectedU - Not affectedE - Not affectedL -Not affectedS - Not affectedMR Status Bits:For destination operand SR:10 - Cleared if bit 8 is specified. Not affected otherwise.11 - Cleared if bit 9 is specified. Not affected otherwise.SO - Cleared if bit 10 is specified. Not affected otherwise.S 1 - Cleared if bit 11 is specified. Not affected otherwise.T - Cleared if bit 13 is specified. Not affected otherwise.DM - Cleared if bit 14 is specified. Not affected otherwiseLF - Cleared if bit 15 is specified. Not affected otherwise.For other destination operands:10 - Not affected11 - Not affectedSO - Not affectedS 1 - Not affectedT - Not affectedDM - Not affectedLF - Not affected
BClRBit Test and ClearBClRInstruction Format:BClR #n,X:eaBClR #n,Y:eaOpcode:23 16 15 8 7 00000101 o 10 1 M M M R R Rio SOb b b b bOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:#n=bit number=bbbbb,ea=6-bit Effective Address=MMMRRREffectiveAddressing Mode MMMRRR Memory SpaceS(Rn)-Nn o 0 Orr X Memory(Rn)+Nn o 0 r r Y Memory(Rn)-o 1 o r r r(Rn)+(Rn)o 1 r r r0 o r r r(Rn+Nn)0 1 r r r-(Rn)1 r r rAbsolute address o 0000Bit Number bbbbb00000•10111where "rrr" refers to an address register RO-R?Timing: 4+mvb oscillator clock cyclesMemory: 1 +ea program words
- Page 240 and 241: LINEAR PREDICTION OF SPEECHJ. D. Ma
- Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
- Page 245 and 246: XnYnTable A-1 Instruction Descripti
- Page 247 and 248: Table A-1 Instruction Description N
- Page 249 and 250: Table A-1 Instruction Description N
- Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
- Page 253 and 254: The address register indirect addre
- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
- Page 259 and 260: Table A-5 Condition Code Computatio
- Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
- Page 263 and 264: ABSAbsolute ValueABSInstruction For
- Page 265 and 266: ADC Add Long with Carry ADCresult.
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289: BCLR Bit Test and Clear BCLRExplana
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
- Page 325 and 326: DIV Divide Interation DIVNote that
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
- Page 339 and 340: ENDDO End Current DO Loop ENDDOExpl
BClRBit Test and ClearBClRInstruction Format:BClR #n,X:eaBClR #n,Y:eaOpcode:23 16 15 8 7 00000101 o 10 1 M M M R R Rio SOb b b b bOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:#n=bit number=bbbbb,ea=6-bit Effective Address=MMMRRREffectiveAddressing Mode MMMRRR Memory SpaceS(Rn)-Nn o 0 Orr X Memory(Rn)+Nn o 0 r r Y Memory(Rn)-o 1 o r r r(Rn)+(Rn)o 1 r r r0 o r r r(Rn+Nn)0 1 r r r-(Rn)1 r r rAbsolute address o 0000Bit Number bbbbb00000•10111where "rrr" refers to an address register RO-R?Timing: 4+mvb oscillator clock cyclesMemory: 1 +ea program words
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