section 7 - Index of
section 7 - Index of section 7 - Index of
BCLR Bit Test and Clear BCLROperation:Assembler Syntax:O[n] -+ C; BelR #n,X:ea0-+ O[n]O[n] -+ C; BelR #n,X:aa0-+ O[n]D[n] -+ C; BClR #n,X:pp0-+ D[n]O[n] -+ C; BelR #n,Y:ea0-+ D[n]D[n] -+ C; BelR #n,Y:aa0-+ D[n]D[n] -+ C; BelR #n,Y:pp0-+ D[n]D[n] -+ C; BelR #n,D0-+ D[n]Description: Test the nth bit of the destination operand 0, clear it and store the result inthe destination location. The state of the nth bit is stored in the carry bit C of the conditioncode register. The bit to be tested is selected by an immediate bit number from 0-23.This instruction performs a read-modify-write operation on the destination location usingtwo destination accesses before releasing the bus. This instruction provides a test-andclearcapability which is useful for synchronizing multiple processors using a sharedmemory. This instruction can use all memory alterable addressing modes.Example:BClR #$E,X:«$FFE4 ;test and clear bit 14 in I/O Port B Data Reg.X:$FFE4
BCLR Bit Test and Clear BCLRExplanation of Example: Prior to execution, the 24-bit X location X:$FFE4 (110 port Bdata register) contains the value $FFFFFF. The execution of the BCLR #$E,X:«$FFE4instruction tests the state of the 14th bit in X:$FFE4, sets the carry bit C accordingly, andthen clears the 14th bit in X:$FFE4.Condition Codes:I: I DM I T I ** JR S1 I so I 11 I : I ..."15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0I LIE I U clR N I z I v I : 1CCR Condition Codes:For destination operand SR:C - Cleared if bit 0 is specified. Not affected otherwise.V - Cleared if bit 1 is specified. Not affected otherwise.Z - Cleared if bit 2 is specified. Not affected. otherwise.N - Cleared if bit 3 is specified. Not affected otherwise.U - Cleared if bit 4 is specified. Not affected otherwise.E - Cleared if bit 5 is specified. Not affected otherwise.L - Cleared if bit 6 is specified. Not affected otherwise.S - Cleared if bit 7 is specified. Not affected otherwise.For destination operand A or B:S -Computed according to the definition. See Notes on page A-55.L - Set if data limiting has occurred. See Notes on page A-55.E - Not affectedU - Not affectedN - Not affectedZ - Not affectedV - Not affectedC - Set if bit tested is set. Cleared otherwise.
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- Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
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- Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
- Page 253 and 254: The address register indirect addre
- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
- Page 259 and 260: Table A-5 Condition Code Computatio
- Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
- Page 263 and 264: ABSAbsolute ValueABSInstruction For
- Page 265 and 266: ADC Add Long with Carry ADCresult.
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287: BCHG Bit Test and Change BCHGNotes:
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
- Page 325 and 326: DIV Divide Interation DIVNote that
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
- Page 335 and 336: DOStart Hardware LoopDOInstruction
- Page 337 and 338: DO Start Hardware Loop DONotes: If
BCLR Bit Test and Clear BCLRExplanation <strong>of</strong> Example: Prior to execution, the 24-bit X location X:$FFE4 (110 port Bdata register) contains the value $FFFFFF. The execution <strong>of</strong> the BCLR #$E,X:«$FFE4instruction tests the state <strong>of</strong> the 14th bit in X:$FFE4, sets the carry bit C accordingly, andthen clears the 14th bit in X:$FFE4.Condition Codes:I: I DM I T I ** JR S1 I so I 11 I : I ..."15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0I LIE I U clR N I z I v I : 1CCR Condition Codes:For destination operand SR:C - Cleared if bit 0 is specified. Not affected otherwise.V - Cleared if bit 1 is specified. Not affected otherwise.Z - Cleared if bit 2 is specified. Not affected. otherwise.N - Cleared if bit 3 is specified. Not affected otherwise.U - Cleared if bit 4 is specified. Not affected otherwise.E - Cleared if bit 5 is specified. Not affected otherwise.L - Cleared if bit 6 is specified. Not affected otherwise.S - Cleared if bit 7 is specified. Not affected otherwise.For destination operand A or B:S -Computed according to the definition. See Notes on page A-55.L - Set if data limiting has occurred. See Notes on page A-55.E - Not affectedU - Not affectedN - Not affectedZ - Not affectedV - Not affectedC - Set if bit tested is set. Cleared otherwise.
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