section 7 - Index of

BCLR Bit Test and Clear BCLROperation:Assembler Syntax:O[n] -+ C; BelR #n,X:ea0-+ O[n]O[n] -+ C; BelR #n,X:aa0-+ O[n]D[n] -+ C; BClR #n,X:pp0-+ D[n]O[n] -+ C; BelR #n,Y:ea0-+ D[n]D[n] -+ C; BelR #n,Y:aa0-+ D[n]D[n] -+ C; BelR #n,Y:pp0-+ D[n]D[n] -+ C; BelR #n,D0-+ D[n]Description: Test the nth bit of the destination operand 0, clear it and store the result inthe destination location. The state of the nth bit is stored in the carry bit C of the conditioncode register. The bit to be tested is selected by an immediate bit number from 0-23.This instruction performs a read-modify-write operation on the destination location usingtwo destination accesses before releasing the bus. This instruction provides a test-andclearcapability which is useful for synchronizing multiple processors using a sharedmemory. This instruction can use all memory alterable addressing modes.Example:BClR #$E,X:«$FFE4 ;test and clear bit 14 in I/O Port B Data Reg.X:$FFE4