section 7 - Index of
section 7 - Index of section 7 - Index of
BCHGBit Test and ChangeBCHGInstruction Format:BCHG #n,X:aaBCHG #n,Y:aaOpcode:23 16 15 8 7\0 0 0 0 1 0 1 1100 a a a a aoSOb b b b blInstruction Fields:#n=bit number=bbbbb,aa=6-bit Absolute Short Address=aaaaaaAbsolute Short Address aaaaaa000000•111111Timing: 4+mvb osci lIator clock cyclesMemory: 1 +ea program wordsMemory SpaceSX Memory 0Y Memory 1Bit Number bbbbb00000•10111
BCHGBit Test and ChangeBCHGInstruction Format:BCHG #n,X:ppBCHG #n,Y:ppOpcode:2310 0 0 0 1 0 116 151 11 0 p p p p p8 7oSOb b b b blInstruction Fields:#n=bit number=bbbbb,ea=6-bit liD Short Address=pppppp1/0 Short Address pppppp Memory SpaceS000000•111111X MemoryY MemoryaBit Number bbbbb00000•10111Timing: 4+mvb oscillator clock cyclesMemory: 1 +ea program words
- Page 234 and 235: DIGITAL SIGNAL PROCESSINGAlan V. Op
- Page 236 and 237: C Programming Language:Controls:. C
- Page 238 and 239: Image Processing:DIGITAL IMAGE PROC
- Page 240 and 241: LINEAR PREDICTION OF SPEECHJ. D. Ma
- Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
- Page 245 and 246: XnYnTable A-1 Instruction Descripti
- Page 247 and 248: Table A-1 Instruction Description N
- Page 249 and 250: Table A-1 Instruction Description N
- Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
- Page 253 and 254: The address register indirect addre
- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
- Page 259 and 260: Table A-5 Condition Code Computatio
- Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
- Page 263 and 264: ABSAbsolute ValueABSInstruction For
- Page 265 and 266: ADC Add Long with Carry ADCresult.
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
- Page 325 and 326: DIV Divide Interation DIVNote that
- Page 327 and 328: DIVInstruction Format:DIV S,DDivide
- Page 329 and 330: DO Start Hardware Loop DOexecuted 6
- Page 331 and 332: DOStart Hardware LoopDOAt LAOther R
- Page 333 and 334: DOStart Hardware LoopDOInstruction
BCHGBit Test and ChangeBCHGInstruction Format:BCHG #n,X:aaBCHG #n,Y:aaOpcode:23 16 15 8 7\0 0 0 0 1 0 1 1100 a a a a aoSOb b b b blInstruction Fields:#n=bit number=bbbbb,aa=6-bit Absolute Short Address=aaaaaaAbsolute Short Address aaaaaa000000•111111Timing: 4+mvb osci lIator clock cyclesMemory: 1 +ea program wordsMemory SpaceSX Memory 0Y Memory 1Bit Number bbbbb00000•10111
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