section 7 - Index of

ASR Arithmetic Shift Accumulator Right ASRCondition Codes:I: I OM 1 T 1** JR S1 1 SO 1 11 1 '~ I: 1 LIE 1 U15 14 13 12 11 10 9 8 7 6 5 4 3 2 0JR N 1 z 1 v 1 ~ IS - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if data limiting occurs during parallel moveE - Set if the signed integer portion of A or B result is in useU - Set if A or B result is un normalizedN - Set if bit 55 of A or B result is setz- Set if A or B result equals zeroV - Always clearedC - Set H bit 0 of A or B was set prior to instruction executionNote: The definitions of the E and U bits vary according to the scaling mode being used.Refer to Section A.5 for complete details.Instruction Format:ASR DOpcode:23 8 7 4 3 oDATA BUS MOVE FIELD I 0 0 Old 0 oOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:D dA 0-BTiming: 2+mv oscillator clock cyclesMemory: 1 +mv program words