section 7 - Index of
section 7 - Index of section 7 - Index of
ANDIAND Immediate with Control RegisterANDIOperation:Assembler Syntax:#xx. D .... DAND(I) #xx,Dwhere • denotes the logical AND operatorDescription: Logically AND the 8-bit immediate operand (#xx) with the contents of thedestination control register D and store the result in the destination control register. Thecondition codes are affected only when the condition code register (CCR) is specified asthe destination operand.Restrictions: The ANDI #xx,MR instruction cannot be used immediately before anENDDO or RTI instruction and cannot be one of the last three instructions in a DO loop(at LA-2, LA-1, or LA).The ANDI #xx,CCR instruction cannot be used immediately before an RTI instruction.Example:AND #$FE,CCR;clear carry bit C in condo code registerBefore ExecutionCCR~I _______ $_3_1 ______ ~After ExecutionCCR~I _______ $_30 ______ ~Explanation of Example: Prior to execution, the 8-bit condition code register (CCR)contains the value $31. The AND #$FE,CCR instruction logically ANDs the immediate 8-bit value $FE with the contents of the condition code register and stores the result in thecondition code register.-
ANDIAND Immediate with Control RegisterANDICondition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2I: I DM I T I·· J:' I so I 11 I '~ I: I LIE I U CCR N I zFor CCR Operand:S - Cleared if bit 7 of the immediate operand is clearedL - Cleared if bit 6 of the immediate operand is clearedE - Cleared if bit 5 of the immediate operand is clearedU - Cleared if bit 4 of the immediate operand is clearedN - Cleared if bit 3 of the immediate operand is clearedZ - Cleared if bit 2 of the immediate operand is clearedV - Cleared if bit 1 of the immediate operand is clearedC - Cleared if bit 0 of the immediate operand is clearedoFor MR and OMR Operands: The condition codes are not affected using these operands.Instruction Format:AND(I) #xx,DOpcode:23 16 1510 0 0 0 0 0 0 o 1 i i8 7 oi 11 o 1 1 1 0 E E IInstruction Fields:#xx=8-bit Immediate Short Data -iii iii i iDEEMR 00CCR 01OMR 10Timing: 2 oscillator clock cyclesMemory: 1 program word
- Page 224 and 225: I Document 10 I Version Synopsis I
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- Page 232 and 233: 11.5 MOTOROLA DSP NEWSThe Motorola
- Page 234 and 235: DIGITAL SIGNAL PROCESSINGAlan V. Op
- Page 236 and 237: C Programming Language:Controls:. C
- Page 238 and 239: Image Processing:DIGITAL IMAGE PROC
- Page 240 and 241: LINEAR PREDICTION OF SPEECHJ. D. Ma
- Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
- Page 245 and 246: XnYnTable A-1 Instruction Descripti
- Page 247 and 248: Table A-1 Instruction Description N
- Page 249 and 250: Table A-1 Instruction Description N
- Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
- Page 253 and 254: The address register indirect addre
- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
- Page 259 and 260: Table A-5 Condition Code Computatio
- Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
- Page 263 and 264: ABSAbsolute ValueABSInstruction For
- Page 265 and 266: ADC Add Long with Carry ADCresult.
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273: ANDLogical ANDANDInstruction Format
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
- Page 321 and 322: DEC Decrement by One DECInstruction
- Page 323 and 324: DIV Divide Interation DIVThe DIV in
ANDIAND Immediate with Control RegisterANDIOperation:Assembler Syntax:#xx. D .... DAND(I) #xx,Dwhere • denotes the logical AND operatorDescription: Logically AND the 8-bit immediate operand (#xx) with the contents <strong>of</strong> thedestination control register D and store the result in the destination control register. Thecondition codes are affected only when the condition code register (CCR) is specified asthe destination operand.Restrictions: The ANDI #xx,MR instruction cannot be used immediately before anENDDO or RTI instruction and cannot be one <strong>of</strong> the last three instructions in a DO loop(at LA-2, LA-1, or LA).The ANDI #xx,CCR instruction cannot be used immediately before an RTI instruction.Example:AND #$FE,CCR;clear carry bit C in condo code registerBefore ExecutionCCR~I _______ $_3_1 ______ ~After ExecutionCCR~I _______ $_30 ______ ~Explanation <strong>of</strong> Example: Prior to execution, the 8-bit condition code register (CCR)contains the value $31. The AND #$FE,CCR instruction logically ANDs the immediate 8-bit value $FE with the contents <strong>of</strong> the condition code register and stores the result in thecondition code register.-