section 7 - Index of

AND Logical AND ANDOperation:S - 0[47:24]-+0[47:24] (parallel move)where -denotes the logical AND operatorAssembler Syntax:AND S,O (parallel move)Description: Logically AND the source operand S with bits 47-24 of the destinationoperand 0 and store the result in bits 47-24 of the destination accumulator. This instructionis a 24-bit operation. The remaining bits of the destination operand 0 are not.affected.Example:AND XO,A 1 (R5)-N5;AND XO with A 1, update R5 using N5Before Executionxo 1-1 _____ $F_F_OO_OO_-"After Executionxol '-________ $_ F_O 0_00 __-"A,-I__$_00_:1_23_4_56_:7_89_A_BC_----.JAI '-___ $_00_:12_0_00_0:7_8_9A_BC __ ~Explanation of Example: Prior to execution, the 24-bit XO register contains the value$FFOOOO, and the 56-bit A accumulator contains the value $00:123456:789ABC. TheAND XO,A instruction logically ANOs the 24-bit value in the XO register with bits 47-24 ofthe A accumulator (A 1) and stores the result in the A accumulator with bits 55-48 and23-0 unchanged.-Condition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 °I LF I DM I T I ** I S1 I SO I 11 I 10 I s I LIE I u I N I z v I :. I.... MR ..... CCR _.S - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if limiting occurs during parallel moveN - Set if bit 47 of A or B result is setZ- Set if bits 47-24 of A or B result are zeroV - Always cleared