section 7 - Index of
section 7 - Index of section 7 - Index of
ADDR Shift Right and Add Accumulators ADDROperation:S+D / 2--tD (parallel move)Assembler Syntax:ADDR S,D (parallel move)Description: Add the source operand S to one-half the destination operand D and storethe result in the destination accumulator. The destination operand D is arithmeticallyshifted one bit to the right while the MS bit of D is held constant prior to the addition operation.In contrast to the ADDL instruction, the carry bit is always set correctly, and theoverflow bit can only be set by the addition operation and not by an overflow due to theinitial shifting operation. This instruction is useful for efficient divide and decimation intime (DIT) FFT algorithms.Example:ADDR 8,A XO,X:(R1)+N1 YO,Y:(R4)-;B+A / 2--tA, save XO and YOBefore ExecutionA '~___$8_0:_00_00_0_0:2_4_68_AC __ ~After ExecutionA ,'----_$_C_0:0_13_57_0_:12_3_45_6_--'B '~ __ $_0_0:0_1_35_70_:0_00_0_00 __ ~B ,$00:013570:000000'-------------~Explanation of Example: Prior to execution, the 56-bit A accumulator contains thevalue $80:000000:2468AC, and the 56-bit 8 accumulator contains the value$00:013570:000000. The ADDR B,A instruction adds one-half the value in the A accumulatorto the value in the B accumulator and stores the 56-bit result in the A accumulator.-
ADDR Shift Right and Add Accumulators ADDRCondition Codes:I LF I OM I T I .. I 8' I 80 I 11I [0 I s I L I E I u I N I z15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0... MR • ~ CCRS - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if limiting (parallel move) or overflow has occurred in resultE - Set if the signed integer portion of A or B result is in useU - Set if A or B result is unnormalizedN - Set if bit 55 of A or B result is setZ- Set if A or B result equals zeroV - Set if overflow has occurred in A or B resultC - Set if a carry (or borrow) occurs from bit 55 of A or B result.Note: The definitions of the E and U bits vary according to the scaling mode being used.Refer to Section A.5 for complete details.Instruction Format:ADDR 8,DOpcode:23 8 7 4 3DATA BUS MOVE FIELD I 0 0 o 0 I dOPTIONAL EFFECTIVE ADDRESS EXTENSIONoooInstruction Fields:S,D dB,A 0A,B 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words-
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- Page 224 and 225: I Document 10 I Version Synopsis I
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- Page 232 and 233: 11.5 MOTOROLA DSP NEWSThe Motorola
- Page 234 and 235: DIGITAL SIGNAL PROCESSINGAlan V. Op
- Page 236 and 237: C Programming Language:Controls:. C
- Page 238 and 239: Image Processing:DIGITAL IMAGE PROC
- Page 240 and 241: LINEAR PREDICTION OF SPEECHJ. D. Ma
- Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
- Page 245 and 246: XnYnTable A-1 Instruction Descripti
- Page 247 and 248: Table A-1 Instruction Description N
- Page 249 and 250: Table A-1 Instruction Description N
- Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
- Page 253 and 254: The address register indirect addre
- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
- Page 259 and 260: Table A-5 Condition Code Computatio
- Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
- Page 263 and 264: ABSAbsolute ValueABSInstruction For
- Page 265 and 266: ADC Add Long with Carry ADCresult.
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269: ADDL Shift Left and Add Accumulator
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
- Page 315 and 316: CMPM Compare Magnitude CMPMConditio
- Page 317 and 318: DEBUGEnter Debug ModeDEBUGOpcode:23
- Page 319 and 320: DEBUGcc Enter Debug Mode Conditiona
ADDR Shift Right and Add Accumulators ADDRCondition Codes:I LF I OM I T I .. I 8' I 80 I 11I [0 I s I L I E I u I N I z15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0... MR • ~ CCRS - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if limiting (parallel move) or overflow has occurred in resultE - Set if the signed integer portion <strong>of</strong> A or B result is in useU - Set if A or B result is unnormalizedN - Set if bit 55 <strong>of</strong> A or B result is setZ- Set if A or B result equals zeroV - Set if overflow has occurred in A or B resultC - Set if a carry (or borrow) occurs from bit 55 <strong>of</strong> A or B result.Note: The definitions <strong>of</strong> the E and U bits vary according to the scaling mode being used.Refer to Section A.5 for complete details.Instruction Format:ADDR 8,DOpcode:23 8 7 4 3DATA BUS MOVE FIELD I 0 0 o 0 I dOPTIONAL EFFECTIVE ADDRESS EXTENSIONoooInstruction Fields:S,D dB,A 0A,B 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words-
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