section 7 - Index of

section 7 - Index of section 7 - Index of

11.07.2015 Views

ADDL Shift Left and Add Accumulators ADDLOperation:S+2*D~D (parallel move)Assembler Syntax:ADDL S,D (parallel move)Description: Add the source operand S to two times the destination operand D andstore the result in the destination accumulator. The destination operand D is arithmeticallyshifted one bit to the left, and a zero is shifted into the LS bit of D prior to the additionoperation. The carry bit is set correctly if the source operand does not overflow as aresult of the left shift operation. The overflow bit may be set as a result of either the shiftingor addition operation (or both). This instruction is useful for efficient divide and decimationin time (DIT) FFT algorithms.Example:ADDL A,B #$O,RO;A+2*B~B, set up addr. reg. ROBefore ExecutionA 1~ ____ $O_O:_OO_OO_O_O:O_O_01_23 __ ~After ExecutionA ~I ___ $_O_O:O_O_OO_OO_:O_OO_12_3 __ ~B ~I ___ $_O_O:_OO_50_00_:0_00_0_00 __ ~BI L-___ $_O_O:O_O_AO_OO_:O_OO_1_23 __ ~Explanation of Example: Prior to execution, the 56-bit accumulator contains the value$00:000000:000123, and the 56-bit B accumulator contains the value$00:005000:000000. The ADDL A,B instruction adds two times the value in the B accumulatorto the value in the A accumulator and stores the 56-bit result in the B accumulator.-

ADDL Shift Left and Add Accumulators ADDLCondition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 01 LF I OM I T I·· I 81 I 80 I 11 lois I LEI U N I z v I :.1.... MR ..... CCR _.S - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if limiting (parallel move) or overflow has occurred in resultE - Set if the signed integer portion of A or B result is in useU - Set if A or B result is unnormalizedN - Set if bit 55 of A or B result is setZ- Set if A or B result equals zeroV - Set If overflow has occurred In A or B result or if the MS bit of the destinationoperand Is changed as a result of the Instruction's left shiftC - Set if a carry (or borrow) occurs from bit 55 of A or B result.Note: The definitions of the E and U bits vary according to the scaling mode being used.Refer to Section A.5 for complete details.Instruction Format:ADDL S,DOpcode:23 8 7DATA BUS MOVE FIELD I 0 04 3 oo 1 I d o oOPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:S,D dB,A 0A,B 1Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words

ADDL Shift Left and Add Accumulators ADDLOperation:S+2*D~D (parallel move)Assembler Syntax:ADDL S,D (parallel move)Description: Add the source operand S to two times the destination operand D andstore the result in the destination accumulator. The destination operand D is arithmeticallyshifted one bit to the left, and a zero is shifted into the LS bit <strong>of</strong> D prior to the additionoperation. The carry bit is set correctly if the source operand does not overflow as aresult <strong>of</strong> the left shift operation. The overflow bit may be set as a result <strong>of</strong> either the shiftingor addition operation (or both). This instruction is useful for efficient divide and decimationin time (DIT) FFT algorithms.Example:ADDL A,B #$O,RO;A+2*B~B, set up addr. reg. ROBefore ExecutionA 1~ ____ $O_O:_OO_OO_O_O:O_O_01_23 __ ~After ExecutionA ~I ___ $_O_O:O_O_OO_OO_:O_OO_12_3 __ ~B ~I ___ $_O_O:_OO_50_00_:0_00_0_00 __ ~BI L-___ $_O_O:O_O_AO_OO_:O_OO_1_23 __ ~Explanation <strong>of</strong> Example: Prior to execution, the 56-bit accumulator contains the value$00:000000:000123, and the 56-bit B accumulator contains the value$00:005000:000000. The ADDL A,B instruction adds two times the value in the B accumulatorto the value in the A accumulator and stores the 56-bit result in the B accumulator.-

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