section 7 - Index of
section 7 - Index of section 7 - Index of
ACC Add Long with Carry ACCOperation:S+C+D -+ D (parallel move)Assembler Syntax:ADC S,D (parallel move)Description: Add the source operand S and the carry bit C of the condition code registerto the destination operand D and store the result in the destination accumulator. Longwords (48 bits) may be added to the (56-bit) destination accumulator.Note: The carry bit is set correctly for multiple precision arithmetic using long-word operandsif the extension register of the destination accumulator (A2 or B2) is the signextension of bit 47 of the destination accumulator (A or B).Example:MOVE L:
ADC Add Long with Carry ADCresult. The actual 96-bit result is stored in memory using the A 10 and B10 operands(instead of A and B) because shifting and limiting is not desired.Condition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I LF I OM I T I ** I 81 I 80 I 11 I lois I I I L E U N I z v I~ MR .~ CCR :.1S - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if limiting (parallel move) or overflow has occurred in resultE - Set if the signed integer portion of A or B result is in useU - Set if A or B result is unnormalizedN - Set if bit 55 of A or B result is setZ- Set if A or B result equals zeroV - Set if overflow has occurred in A or B resultC - Set if a carry (or borrow) occurs from bit 55 of A or B result.Note: The definitions of the E and U bits vary according to the scaling mode being used.Refer to Section A.5 for complete details.Instruction Format:ADC S,DOpcode:23 8 74 3 0DATA BUS MOVE FIELD 1 0 0OPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:S,D JdX,A 00X,B 01V,A 10V,B 1 1-Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words
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- Page 222 and 223: • In-line assembler language code
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- Page 232 and 233: 11.5 MOTOROLA DSP NEWSThe Motorola
- Page 234 and 235: DIGITAL SIGNAL PROCESSINGAlan V. Op
- Page 236 and 237: C Programming Language:Controls:. C
- Page 238 and 239: Image Processing:DIGITAL IMAGE PROC
- Page 240 and 241: LINEAR PREDICTION OF SPEECHJ. D. Ma
- Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
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- Page 251 and 252: Table A-2 DSP56K Addressing ModesAd
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- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
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- Page 263: ABSAbsolute ValueABSInstruction For
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
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- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
- Page 303 and 304: BSET Bit Test and Set BSETNotes: If
- Page 305 and 306: BTSTBit TestBTSTCondition Codes:115
- Page 307 and 308: 8TSTBit Test8TSTInstruction Format:
- Page 309 and 310: 8TSTBit Test8TSTInstruction Format:
- Page 311 and 312: CLRClear AccumulatorCLRInstruction
- Page 313 and 314: CMP Compare CMPCondition Codes:15 1
ADC Add Long with Carry ADCresult. The actual 96-bit result is stored in memory using the A 10 and B10 operands(instead <strong>of</strong> A and B) because shifting and limiting is not desired.Condition Codes:15 14 13 12 11 10 9 8 7 6 5 4 3 2 0I LF I OM I T I ** I 81 I 80 I 11 I lois I I I L E U N I z v I~ MR .~ CCR :.1S - Computed according to the definition in A.5 CONDITION CODE COMPUTATIONL - Set if limiting (parallel move) or overflow has occurred in resultE - Set if the signed integer portion <strong>of</strong> A or B result is in useU - Set if A or B result is unnormalizedN - Set if bit 55 <strong>of</strong> A or B result is setZ- Set if A or B result equals zeroV - Set if overflow has occurred in A or B resultC - Set if a carry (or borrow) occurs from bit 55 <strong>of</strong> A or B result.Note: The definitions <strong>of</strong> the E and U bits vary according to the scaling mode being used.Refer to Section A.5 for complete details.Instruction Format:ADC S,DOpcode:23 8 74 3 0DATA BUS MOVE FIELD 1 0 0OPTIONAL EFFECTIVE ADDRESS EXTENSIONInstruction Fields:S,D JdX,A 00X,B 01V,A 10V,B 1 1-Timing: 2+mv oscillator clock cyclesMemory: 1 +mv program words
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