section 7 - Index of
section 7 - Index of section 7 - Index of
Table A-4 Addressing Mode Modifier SummaryBinary MO-M7 Hex MO-M7 Addressing Mode Arithmetic0000 0000 0000 0000 0000 Reverse Carry (Bit Reverse)0000 0000 0000 0001 0001 Modulo 200000000 0000 0010 0002 Modulo 30111111111111110 7FFE Modulo 327670111 1111 1111 1111 7FFF Modulo 327681 000 0000 0000 0000 8000 Reserved1000 0000 0000 0001 8001 Multiple Wrap-Around Modulo 21000 0000 0000 0010 8002 Reserved1000000000000011 8003 Multiple Wrap-Around Modulo 4Reserved1 000 0000 0000 0111 8007 Multiple Wrap-Around Modulo 8Reserved1000000000001111 800F Multiple Wrap-Around Modulo 24Reserved100000000001 1111 801F Multiple Wrap-Around Modulo 2 5Reserved100000000011 1111 803F Multiple Wrap-Around Modulo 2 6Reserved100000000111 1111 807F Multiple Wrap-Around Modulo 27Reserved1000 0000 1111 1111 80FF Multiple Wrap-Around Modulo 2 8Reserved10000001 1111 1111 81FF Multiple Wrap-Around Modulo 2 9Reserved1000 0011 1111 1111 83FF Multiple Wrap-Around Modulo 2 10-Reserved10000111 1111 1111 87FF Multiple Wrap-Around Modulo 211Reserved1000 1111 1111 1111 8FFF Multiple Wrap-Around Modulo 212Reserved1001 1111 1111 1111 9FFF Multiple Wrap-Around Modulo 2 13Reserved1011111111111111 BFFF Multiple Wrap-Around Modulo 214Reserved1111 1111 11111111 FFFF Linear (Modulo 2 15 )
A.SCONDITION CODE COMPUTATION15 14 13 12 11 10 9 8 7 6 4 3 2 oI'F 10M I T I ** I 51 I SO I 11 I 10 I 5 I l I E I u N I z.. MA .. oC eeAThe condition code register (CCR) portion of the status register (SR) consists of eightdefined bits:S -L -Scaling BitLimit BitN -Z -Negative BitZero BitE - Extension Bit V - Overflow BitU - Unnormalized Bit C - Carry BitThe E, U, N, Z, V, and C bits are true condition code bits that reflect the condition of theresult of a data ALU operation. These condition code bits are not latched and are notaffected by address ALU calculations or by data transfers over the X, Y, or globaldata buses. The L bit is a latching overflow bit which indicates that an overflow hasoccurred in the data ALU or that data limiting has occurred when moving the contents ofthe A and/or B accumulators. The S bit is a latching bit used in block floating pOint operationsto indicate the need to scale the number in A or B. See SECTION 5 - PROGRAMCONTROL UNIT for information on the MR portion of the status register.The standard definition of the condition code bits follows. Exceptions to these standarddefinitions are given in the notes which follow Table A-5.
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- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
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Table A-4 Addressing Mode Modifier SummaryBinary MO-M7 Hex MO-M7 Addressing Mode Arithmetic0000 0000 0000 0000 0000 Reverse Carry (Bit Reverse)0000 0000 0000 0001 0001 Modulo 200000000 0000 0010 0002 Modulo 30111111111111110 7FFE Modulo 327670111 1111 1111 1111 7FFF Modulo 327681 000 0000 0000 0000 8000 Reserved1000 0000 0000 0001 8001 Multiple Wrap-Around Modulo 21000 0000 0000 0010 8002 Reserved1000000000000011 8003 Multiple Wrap-Around Modulo 4Reserved1 000 0000 0000 0111 8007 Multiple Wrap-Around Modulo 8Reserved1000000000001111 800F Multiple Wrap-Around Modulo 24Reserved100000000001 1111 801F Multiple Wrap-Around Modulo 2 5Reserved100000000011 1111 803F Multiple Wrap-Around Modulo 2 6Reserved100000000111 1111 807F Multiple Wrap-Around Modulo 27Reserved1000 0000 1111 1111 80FF Multiple Wrap-Around Modulo 2 8Reserved10000001 1111 1111 81FF Multiple Wrap-Around Modulo 2 9Reserved1000 0011 1111 1111 83FF Multiple Wrap-Around Modulo 2 10-Reserved10000111 1111 1111 87FF Multiple Wrap-Around Modulo 211Reserved1000 1111 1111 1111 8FFF Multiple Wrap-Around Modulo 212Reserved1001 1111 1111 1111 9FFF Multiple Wrap-Around Modulo 2 13Reserved1011111111111111 BFFF Multiple Wrap-Around Modulo 214Reserved1111 1111 11111111 FFFF Linear (Modulo 2 15 )
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