section 7 - Index of
section 7 - Index of section 7 - Index of
Addressing ModeTable A-3 DSP56K Addressing Mode EncodingMode RegAddressing Categories AssemblerMMM RRRU P M ASyntaxRegister DirectData or Control Register - - X (See Table A-1)Address Register - - X RnAddress Offset Register - - X NnAddress Modifier Register - - X MnAddress Register IndirectNo Update 100 Rn X X X (Rn)Postincrement by 1 011 Rn X X X X (Rn) +Postdecrement by 1 010 Rn X X X X (Rn) -Postincrement by Offset Nn 001 Rn X X X X (Rn) + NnPostdecrement by Offset Nn 000 Rn X X X (RN) - NnIndexed by Offset Nn 101 Rn X X (Rn + Nn).Predecrement by 1 111 Rn X X - (Rn)SpecialImmediate Data 110 100 X #xxxxxxAbsolute Address 110 000 X X xxxxImmediate Short Data - - #xxShort Jump Address - - X xxxAbsolute Short Address - - X aaI/O Short Address - - X ppImplicit - - X-. Update Mode (U) - Modifies address registers without any associated data move.Parallel Mode (P) - Used in instructions where two effective addresses are required.Memory Mode (M) - Refers to operands in memory using an effective addressing field.Alterable Mode (A) - Refers to alterable or writable registers or memory.
The address register indirect addressing modes require that the offset register numberbe the same as the address register number. The assembler syntax "N" may be usedinstead of liNn" in the address register indirect memory addressing modes. If "N" is specified,the offset register number is the same as the address register number.A.4.1 Addressing Mode ModifiersThe addressing mode selected in the instruction word is further specified by the contentsof the address modifier register Mn. The addressing mode update modifiers (MO-M7) areshown in Table A-4. There are no restrictions on the use of modifier types with anyaddress register indirect addressing mode.-
- Page 201 and 202: 10.3.4.4 Software Debug Occurrence
- Page 203 and 204: 10.4.4 Memory High Address Comparat
- Page 205 and 206: 10.6.1 External Debug Request Durin
- Page 207 and 208: PABCIRCULARBUFFERPOINTERDSCKDSOFigu
- Page 209 and 210: are serially available to the exter
- Page 211 and 212: k. ACKI. ClKm. Send command READ FI
- Page 213 and 214: 19. ACK20. Send command READ GDB RE
- Page 215 and 216: 10.11.6.1 Case 1: Return To The Pre
- Page 217: SECTION 11ADDITIONAL SUPPORTDr. BuB
- Page 220 and 221: The following is a partial list of
- Page 222 and 223: • In-line assembler language code
- Page 224 and 225: I Document 10 I Version Synopsis I
- Page 226 and 227: I Document 10 I Version Synopsis I
- Page 228 and 229: I Document ID I Version Synopsis I
- Page 230 and 231: I Document 10 I Version Synopsis I
- Page 232 and 233: 11.5 MOTOROLA DSP NEWSThe Motorola
- Page 234 and 235: DIGITAL SIGNAL PROCESSINGAlan V. Op
- Page 236 and 237: C Programming Language:Controls:. C
- Page 238 and 239: Image Processing:DIGITAL IMAGE PROC
- Page 240 and 241: LINEAR PREDICTION OF SPEECHJ. D. Ma
- Page 243 and 244: A.1 APPENDIX A INTRODUCTIONThis app
- Page 245 and 246: XnYnTable A-1 Instruction Descripti
- Page 247 and 248: Table A-1 Instruction Description N
- Page 249 and 250: Table A-1 Instruction Description N
- Page 251: Table A-2 DSP56K Addressing ModesAd
- Page 255 and 256: A.SCONDITION CODE COMPUTATION15 14
- Page 257 and 258: S1 SO Scaling Mode Signed Integer P
- Page 259 and 260: Table A-5 Condition Code Computatio
- Page 261 and 262: A.7 INSTRUCTION DESCRIPTIONSThe fol
- Page 263 and 264: ABSAbsolute ValueABSInstruction For
- Page 265 and 266: ADC Add Long with Carry ADCresult.
- Page 267 and 268: ADD Add ADDCondition Codes:15 14 13
- Page 269 and 270: ADDL Shift Left and Add Accumulator
- Page 271 and 272: ADDR Shift Right and Add Accumulato
- Page 273 and 274: ANDLogical ANDANDInstruction Format
- Page 275 and 276: ANDIAND Immediate with Control Regi
- Page 277 and 278: ASL Arithmetic Shift Accumulator Le
- Page 279 and 280: ASR Arithmetic Shift Accumulator Ri
- Page 281 and 282: BCHG Bit Test and Change BCHGExplan
- Page 283 and 284: BCHGBit Test and ChangeBCHGInstruct
- Page 285 and 286: BCHGBit Test and ChangeBCHGInstruct
- Page 287 and 288: BCHG Bit Test and Change BCHGNotes:
- Page 289 and 290: BCLR Bit Test and Clear BCLRExplana
- Page 291 and 292: BClRBit Test and ClearBClRInstructi
- Page 293 and 294: BClRBit Test and ClearBClRInstructi
- Page 295 and 296: BClR Bit Test and Clear BClRNotes:
- Page 297 and 298: BSET Bit Test and Set BSETExplanati
- Page 299 and 300: BSETBit Test and SetBSETInstruction
- Page 301 and 302: BSETBit Test and SetBSETInstruction
Addressing ModeTable A-3 DSP56K Addressing Mode EncodingMode RegAddressing Categories AssemblerMMM RRRU P M ASyntaxRegister DirectData or Control Register - - X (See Table A-1)Address Register - - X RnAddress Offset Register - - X NnAddress Modifier Register - - X MnAddress Register IndirectNo Update 100 Rn X X X (Rn)Postincrement by 1 011 Rn X X X X (Rn) +Postdecrement by 1 010 Rn X X X X (Rn) -Postincrement by Offset Nn 001 Rn X X X X (Rn) + NnPostdecrement by Offset Nn 000 Rn X X X (RN) - Nn<strong>Index</strong>ed by Offset Nn 101 Rn X X (Rn + Nn).Predecrement by 1 111 Rn X X - (Rn)SpecialImmediate Data 110 100 X #xxxxxxAbsolute Address 110 000 X X xxxxImmediate Short Data - - #xxShort Jump Address - - X xxxAbsolute Short Address - - X aaI/O Short Address - - X ppImplicit - - X-. Update Mode (U) - Modifies address registers without any associated data move.Parallel Mode (P) - Used in instructions where two effective addresses are required.Memory Mode (M) - Refers to operands in memory using an effective addressing field.Alterable Mode (A) - Refers to alterable or writable registers or memory.
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