section 7 - Index of
section 7 - Index of section 7 - Index of
PDS contains the second word of the jump as required for the jump instruction execution.The EX bit causes the OnCE controller to release the chip from the debugmode and the status bits in OSCR are cleared. The GO bit causes the chip to startexecuting the jump instruction which will then cause the chip to continue instructionexecution from the target address. Note that the trace counter will count the jumpinstruction so the current trace counter may need to be corrected if the trace modeis enabled.10.11.7 Debugging Multiprocessor Systems With a Single External CommandControllerIn multiprocessor systems, each processor may be individually debugged as describedabove. When simultaneous exit of the debug state is desired for more than one processor,each processor must first be loaded with the required PIL and PDS values where processingshould proceed. This is accomplished by the following sequence as applied to eachprocessor:..1. Send command WRITE PDS REGISTER, no GO, no EX (00001001)The OnCE controller selects PDS as destination for serial data. Also, the OnCEcontroller selects the on-chip PAS register as the source for the PAS bus.2.ACK3. Send 24 bits of either the opcode of a 2-word jump instruction or the saved PIL value.After the 24 bits have been received, the PDS register drives the PDS. TheOnCE controller causes the PIL to latch the PDS value.4.ACK5. Send command WRITE PDS REGISTER, no GO, no EX (00001001)The OnCE controller selects PDS as destination for serial data .6.ACK7. Send 24 bits of either the jump target absolute address ($xxxxxx) or the saved PDSvalue. After 24 bits have been received, the PDS register drives the PDS.8.ACKAt this point, all processors should have the required PIL and PDS values while still in debugmode. To return all processors to the normal execution state simultaneously, the followingcommand should be issued to all processors in parallel:9. Send command NO REGISTER SELECTED, GO, EX (01111111)The OnCE controller releases the chips from the debug mode and instruction executionis resumed.
SECTION 11ADDITIONAL SUPPORTDr. BuB Electronic Bulletin BoardU)~::s~~8'" .- 01a. f!! cI Q)'_:g.~.~CocCo~..cc~011-.- a. a. a. a. a.~cncncncncncccccc-
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