section 7 - Index of
section 7 - Index of section 7 - Index of
To initiate the trace mode of operation, the counter is loaded with a value, the programcounter is set to the start location of the instruction(s) to be executed real-time, the TMEbit is set in the OSCR, and the processor exits the debug mode by executing the appropriatecommand issued by the external command controller.Upon exiting the debug mode, the counter is decremented after each execution of an instruction.Interrupts are serviceable, and all instructions executed (including fast interruptservices and the execution of each repeated instruction) will decrement the trace counter.Upon decrementing the trace counter to zero, the processor will re-enter the debug mode,the trace occurrence bit TO in the OSCR will be set, and the DSO pin 'will be toggled toindicate that the processor has entered debug mode and is requesting service (ISTRACEasserted).END OF INSTRUCTIONDSIDSO~-----1DSCKTRACE COUNTERCOUNT=OISTRACE-Figure 10-7 OnCE,Trace Logic Block Diagram10.5.1 Trace Counter (OTC)The OTC is a 24-bit counter that can be read, written, or cleared through the OnCE serialinterface. If N instructions are to be executed before entering the debug mode, the TraceCounter should be loaded with N-1. The Trace Counter is cleared by hardware reset.10.6 METHODS OF ENTERING THE DEBUG MODEThe chip acknowledges having entered the debug mode by pulsing low the DSO line, informingthe external command controller that the chip has entered the debug mode andis waiting for commands.The following paragraphs discuss conditions that bring the processorinto the debug mode.
10.6.1 External Debug Request During RESETHolding the DR line asserted during the assertion of RESET causes the chip to enter thedebug mode. After receiving the acknowledge, the external command controller mustdeassert the DR line before sending the first command. Note that in this case the chipdoes not execute any instruction before entering the debug mode.10.6.2 External Debug Request During Normal ActivityHolding the DR line asserted during normal chip activity causes the chip to finish the executionof the current instruction and then enter the debug mode. After receiving the acknowledge,the external command controller must deassert the DR line before sendingthe first command. Note that in this case the chip completes the execution of the currentinstruction and stops after the newly fetched instruction enters the instruction latch. Thisprocess is the same for any newly fetched instruction including instructions fetched by theinterrupt processing, or those that will be aborted by the interrupt processing.10.6.3 External Debug Request During STOPAsserting DR when the chip is in the stop state (i. e., has executed a STOP instruction)and keeping it asserted until an acknowledge pulse in DSO is produced causes the chipto exit the stop state and enter the debug mode. After receiving the acknowledge, the externalcommand controller must deassert DR before sending the first command. Note thatin this case, the chip completes the execution of the STOP instruction and halts after thenext instruction enters the instruction latch.10.6.4 External Debug Request During WAITAsserting DR when the chip is in the wait state (i. e., has executed a WAIT instruction)and keeping it asserted until an acknowledge pulse in DSO is produced causes the chipto exit the wait state and enter the debug mode. After receiving the acknowledge, the externalcommand controller must deassert DR before sending the first command. Note thatin this case, the chip completes the execution of the WAIT instruction and halts after thenext instruction enters the instruction latch.-10.6.5 Software Request During Normal Activity, Upon executing the DEBUG or DEBUGcc instruction when the specified condition is true,the chip enters the debug mode after the instruction following the DEBUG instruction hasentered the instruction latch.10.6.6 Enabling Trace ModeWhen the trace mode mechanism is enabled and the trace counter is greater than zero,
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10.6.1 External Debug Request During RESETHolding the DR line asserted during the assertion <strong>of</strong> RESET causes the chip to enter thedebug mode. After receiving the acknowledge, the external command controller mustdeassert the DR line before sending the first command. Note that in this case the chipdoes not execute any instruction before entering the debug mode.10.6.2 External Debug Request During Normal ActivityHolding the DR line asserted during normal chip activity causes the chip to finish the execution<strong>of</strong> the current instruction and then enter the debug mode. After receiving the acknowledge,the external command controller must deassert the DR line before sendingthe first command. Note that in this case the chip completes the execution <strong>of</strong> the currentinstruction and stops after the newly fetched instruction enters the instruction latch. Thisprocess is the same for any newly fetched instruction including instructions fetched by theinterrupt processing, or those that will be aborted by the interrupt processing.10.6.3 External Debug Request During STOPAsserting DR when the chip is in the stop state (i. e., has executed a STOP instruction)and keeping it asserted until an acknowledge pulse in DSO is produced causes the chipto exit the stop state and enter the debug mode. After receiving the acknowledge, the externalcommand controller must deassert DR before sending the first command. Note thatin this case, the chip completes the execution <strong>of</strong> the STOP instruction and halts after thenext instruction enters the instruction latch.10.6.4 External Debug Request During WAITAsserting DR when the chip is in the wait state (i. e., has executed a WAIT instruction)and keeping it asserted until an acknowledge pulse in DSO is produced causes the chipto exit the wait state and enter the debug mode. After receiving the acknowledge, the externalcommand controller must deassert DR before sending the first command. Note thatin this case, the chip completes the execution <strong>of</strong> the WAIT instruction and halts after thenext instruction enters the instruction latch.-10.6.5 S<strong>of</strong>tware Request During Normal Activity, Upon executing the DEBUG or DEBUGcc instruction when the specified condition is true,the chip enters the debug mode after the instruction following the DEBUG instruction hasentered the instruction latch.10.6.6 Enabling Trace ModeWhen the trace mode mechanism is enabled and the trace counter is greater than zero,
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