section 7 - Index of
section 7 - Index of section 7 - Index of
When BC3-BCO=0011, program memory breakpoints are enabled for any read or writeaccess to the Program space (any kind of MOVE, true and false fetches, fetches of secondword, etc.).When BC3-BCO=01 00, program memory breakpoints are enabled only for fetches of thefirst instruction word of instructions that are actually executed. Aborted instructions andprefetched instructions that are discarded (such as jump targets that are not taken) areignored by the breakpoint logic.When BC3-BCO=01 01,0110 or 0111, program memory breakpoints are enabled only forexplicit program memory access resulting from MOVEP or MOVEM instructions to/fromP: memory space.Table 10-3 Memory Breakpoint Control TableBC3 BC2 BC1 BCO DESCRIPTION-0 0 0 0 Breakpoint disabled0 0 0 1 Breakpoint on any fetch (including aborted instructions)0 0 1 0 Breakpoint on any P read (any fetch or move)0 0 1 1 Breakpoint on any P access (any fetch, P move R/W)0 1 0 0 Breakpoint on executed fetches only0 1 0 1 Breakpoint on P space write0 1 1 0 Breakpoint on P space read (no fetches)0 1 1 1 Breakpoint on P space write or read (no fetches)1 0 0 0 Reserved1 0 0 1 Breakpoint on X space write1 0 1 0 Breakpoint on X space read1 0 1 1 Breakpoint on X space write or read1 1 0 0 Reserved1 1 0 1 Breakpoint on Y space write1 1 1 0 Breakpoint on Y space read1 1 1 1 Breakpoint on Y space write or read10.3.4.2 Trace Mode Enable (TME) Bit 4The TME control bit, when set, enables the Trace Mode of operation (see Section 10.5).This bit is cleared on hardware reset.10.3.4.3 Reserved (Bits 5-7,11-15)These bits are reserved for future use. They read as zero and should be written with zerofor future compatibility.
10.3.4.4 Software Debug Occurrence (SWO) Bit 8This read-only status bit is set when the processor enters debug mode of operation as aresult of the execution of the DEBUG or DEBUGcc instruction with condition true. This bitis cleared on hardware reset or when leaving the debug mode with the GO and EX bitsset.10.3.4.5 Memory Breakpoint Occurrence (MBO) Bit 9This read-only status bit is set when a memory breakpoint occurs. This bit is cleared onhardware reset or when leaving the debug mode with the GO and EX bits set.10.3.4.6 Trace Occurrence (TO) Bit 10This read-only status bit is set when the processor enters debug mode of operation, whenthe trace counter is zero and the trace mode has been armed. This bit is cleared on hardwarereset or when leaving the debug mode with the GO and EX bits set.10.4 OnCE MEMORY BREAKPOINT LOGICMemory breakpOints may be set on program memory or data memory locations. Also, thebreakpoint does not have to be in a specific memory address but within an address rangeof where the program may be executing. This Significantly increases the programmer'sability to monitor what the program is doing in real-time.The breakpOint logic contains a latch for the addresses, registers that store the upper andlower address limit, comparators, and a breakpoint counter. Figure 10-6 illustrates theblock diagram of the OnCE Memory Breakpoint Logic.Address comparators help to determine where a program may be getting lost or whendata is being written to areas that should not be written to. They are also useful in haltinga program at a specific point to examine/change registers or memory. Using address comparatorsto set breakpoints enables the user to set breakpoints in RAM or ROM in any operatingmode. Memory accesses are monitored according to the contents of the OSCR.The low address comparator will generate a logic true signal when the address on the busis greater than or equal to the contents of the lower limit register. The high address comparatorwill generate a logic true Signal when the address on the bus is less than or equalto the contents of the upper limit register. If the low address comparator and high addresscomparator both issue a logiC true signal, the address is within the address range and thebreakpoint counter is decremented if the contents are greater than zero. If zero, thecounter is not decremented and the breakpoint exception occurs (ISBKPT asserted).-10.4.1 Memory Address Latch (OMAL)The Memory Address Latch is a 16-bit register that latches the PAB, XAB or VAB on everyinstruction cycle according to the BC3-BCO bits in OSCR.
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When BC3-BCO=0011, program memory breakpoints are enabled for any read or writeaccess to the Program space (any kind <strong>of</strong> MOVE, true and false fetches, fetches <strong>of</strong> secondword, etc.).When BC3-BCO=01 00, program memory breakpoints are enabled only for fetches <strong>of</strong> thefirst instruction word <strong>of</strong> instructions that are actually executed. Aborted instructions andprefetched instructions that are discarded (such as jump targets that are not taken) areignored by the breakpoint logic.When BC3-BCO=01 01,0110 or 0111, program memory breakpoints are enabled only forexplicit program memory access resulting from MOVEP or MOVEM instructions to/fromP: memory space.Table 10-3 Memory Breakpoint Control TableBC3 BC2 BC1 BCO DESCRIPTION-0 0 0 0 Breakpoint disabled0 0 0 1 Breakpoint on any fetch (including aborted instructions)0 0 1 0 Breakpoint on any P read (any fetch or move)0 0 1 1 Breakpoint on any P access (any fetch, P move R/W)0 1 0 0 Breakpoint on executed fetches only0 1 0 1 Breakpoint on P space write0 1 1 0 Breakpoint on P space read (no fetches)0 1 1 1 Breakpoint on P space write or read (no fetches)1 0 0 0 Reserved1 0 0 1 Breakpoint on X space write1 0 1 0 Breakpoint on X space read1 0 1 1 Breakpoint on X space write or read1 1 0 0 Reserved1 1 0 1 Breakpoint on Y space write1 1 1 0 Breakpoint on Y space read1 1 1 1 Breakpoint on Y space write or read10.3.4.2 Trace Mode Enable (TME) Bit 4The TME control bit, when set, enables the Trace Mode <strong>of</strong> operation (see Section 10.5).This bit is cleared on hardware reset.10.3.4.3 Reserved (Bits 5-7,11-15)These bits are reserved for future use. They read as zero and should be written with zer<strong>of</strong>or future compatibility.
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