section 7 - Index of

10.3.1.2 Exit Command (EX) Bit 5If the EX bit is set, the processor will leave the debug mode and resume normal operation.The Exit command is executed only if the Go command is issued, and the operation iswrite to OPDBR or read/write to "No Register Selected". Otherwise the EX bit is ignored.EXAction0 Remain in debug mode1 Leave debug mode10.3.1.3 Go Command (GO) Bit 6If the GO bit is set, the chip will execute the instruction which resides in the PIL register.To execute the instruction, the processor leaves the debug mode, and the status is reflectedin the OSO-OS1 pins. The processor will return to the debug mode immediately afterexecuting the instruction if the EX bit is cleared. The processor goes on to normal operationif the EX bit is set. The GO command is executed only if the operation is write toOPDBR or read/write to "No Register Selected". Otherwise the GO bit is ignored.GOAction0 Inactive (no action taken)1 Execute instruction in PIL10.3.1.4 ReadlWrite Command (RIW) Bit 7The RIW bit specifies the direction of data transfer. The table below describes the optionsdefined by the RIW bit.RIWAction0 Write the data associated with the command into the registerspecified by RS4-RSO1 Read the data contained in the register specified by RS4-RSO10.3.2 OnCE Bit Counter (OBC)The OBC is a 5-bit counter associated with shifting in and out the data bits. The OBC isincremented by the falling edges of the DSCK. The OBC is cleared during hardware resetand whenever the DSP56K acknowledges that the debug mode has been entered. TheOBC supplies two signals to the OnCE Decoder: one indicating that the first 8 bits were