section 7 - Index of
section 7 - Index of section 7 - Index of
10.2.4 Debug Request Input (DR)The debug request input (DR) allows the user to enter the debug mode of operation fromthe external command controller. When DR is asserted, it causes the DSP56K to finishthe current instruction being executed, save the instruction pipeline information, enter thedebug mode, and wait for commands to be entered from the DSI line. While in debugmode, the DR pin lets the user reset the OnCE controller by asserting it and deassertingit after receiving acknowledge. It may be necessary to reset the OnCE controller in caseswhere synchronization between the OnCE controller and external circuitry is lost. DR mustbe deasserted after the OnCE responds with an acknowledge on the DSO pin and beforesending the first OnCE command. Asserting DR will cause the chip to exit the STOP orWAIT state.10.3 OnCE CONTROLLER AND SERIAL INTERFACEThe OnCE Controller and Serial Interface contains the following blocks: OnCE commandregister, bit counter, OnCE decoder, and the status/control register. Figure 10-3 illustratesa block diagram of the OnCE controller and serial interface10.3.1 OnCE Command Register (OCR)The OCR is an a-bit shift register that receives its serial data from the DSI pin. It holds thea-bit commands to be used as input for the OnCE Decoder. The Command Register isshown in Figure 10-4.~------------------~~----------~--DSIOnCE COMMAND REGISTERr----t-..-DSCK-ISBKPTISSWDBGOnCE DECODERDSOREG READ REG WRITE MODE SELECTFigure 10-3 OnCE Controller and Serial Interface
76543210I R/W I GO I EX I RS41 RS31 RS21 RS 1 I RSO IFigure 10-4 OnCE Command Register10.3.1.1 Register Select (RS4-RSO) Bits 0-4The Register Select bits define which register is source (destination) for the read (write)operation. Table 10-2 indicates the OnCE register addresses.Table 10-2 OnCE Register AddressingRS4-RSORegister Selected00000 OnCE Status and Control Register (OSCR)00001 Memory Breakpoint Counter (OMBC)00010 Reserved00011 Trace Counter (OTC)00100 Reserved00101 Reserved00110 Memory Upper Limit Register (OMULR)00111 Memory Lower Limit Register (OMLLR)01000 GDB Register (OGDBR)01001 PDB Register (OPDBR)01010 PAB Register for Fetch (OPABFR)01011 PIL Register (OPILR)01100 Clear Memory Breakpoint Counter (OMBC)01101 Reserved01110 Clear Trace Counter (OTC)01111 Reserved10000 Reserved10001 Program Address Bus FIFO and Increment Counter10010 Reserved10011 PAB Register for Decode (OPABDR)101xx Reserved11xxO Reserved11xOx Reserved110xx Reserved11111 No Register Selected-
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76543210I R/W I GO I EX I RS41 RS31 RS21 RS 1 I RSO IFigure 10-4 OnCE Command Register10.3.1.1 Register Select (RS4-RSO) Bits 0-4The Register Select bits define which register is source (destination) for the read (write)operation. Table 10-2 indicates the OnCE register addresses.Table 10-2 OnCE Register AddressingRS4-RSORegister Selected00000 OnCE Status and Control Register (OSCR)00001 Memory Breakpoint Counter (OMBC)00010 Reserved00011 Trace Counter (OTC)00100 Reserved00101 Reserved00110 Memory Upper Limit Register (OMULR)00111 Memory Lower Limit Register (OMLLR)01000 GDB Register (OGDBR)01001 PDB Register (OPDBR)01010 PAB Register for Fetch (OPABFR)01011 PIL Register (OPILR)01100 Clear Memory Breakpoint Counter (OMBC)01101 Reserved01110 Clear Trace Counter (OTC)01111 Reserved10000 Reserved10001 Program Address Bus FIFO and Increment Counter10010 Reserved10011 PAB Register for Decode (OPABDR)101xx Reserved11xxO Reserved11xOx Reserved110xx Reserved11111 No Register Selected-
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