section 7 - Index of
section 7 - Index of section 7 - Index of
...I~W:I:0...ffi~0...0...24-BitS6KModuleX MEMORYRAM/ROMEXPANSIONADDRESS ~-I-II-~:::::'--I--I-----L..-I--.-J EXTERNAL wGENERATION ADDRESS 1-4--~UNIT ~r-II-"':"':";=----I----- I--~ BUSo«SWITCHCf)Cf)BUSCONTROL 14--B--_t-«~o0...INTERNALEXTERNALD~A ~.I.'-----I--.II--"II.~----"~"----.T.--~DATABUSSW~HSWITCH ~ ... ~C:(-MODBIIROBMODAIIROARESETDATAALU24X24+56~56-BIT MACTWO 56-BIT ACCUMULATOR_ 16 BITS-24 BITSFigure 10-2 DSP56K Block DiagramDSI/OSO pin is an output when the processor is not in debug mode. When switching fromoutput to input, the pin is three-stated. During hardware reset, this pin is defined as an outputand it is driven low.Note: To avoid possible glitches, an external pull-down resistor should be attached to thispin.
10.2.2 Debug Serial Clock/Chip Status 1 (DSCK/OS1)The DSCK/OS 1 pin supplies the serial clock to the OnCE when it is an input. The serialclock provides pulses required to shift data into and out of the OnCE serial port. (Data isclocked into the OnCE on the falling edge and is clocked out of the OnCE serial port onthe rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processorclock frequency. When an output, this pin, in conjunction with the OSO pin,provides information about the chip status (see Table 10-1). The DSCK/OS1 pin is an outputwhen the chip is not in debug mode. When switching from output to input, the pin isthree-stated. During hardware reset, this pin is defined as an output and it is driven low.Note: To avoid possible glitches, an external pull-down resistor should be attached to thispin.Table 10-1 Chip Status InformationOS1 OSO Status0 0 Normal State0 1 Stop or Wait State1 0 Chip waits for bus mastership1 1 Chip waits for end of memory wait states(due to WT assertion or BCR)10.2.3 Debug Setial Output (DSO)Serial data is read from the OnCE through the DSO pin, as specified by the last commandreceived from the external command controller. Data is always shifted out the OnCE serialport most significant bit (MSB) first. Data is clocked out of the OnCE serial port on the risingedge of DSCK.The DSO pin also provides acknowledge pulses to the external command controller.When the chip enters the debug mode, the DSO pin will be pulsed low to indicate (acknowledge)that the OnCE is waiting for commands. After receiving a read command, theDSO pin will be pulsed low to indicate that the requested data is available and the OnCEserial port is ready to receive clocks in order to deliver the data. After receiving a writecommand, the DSO pin will be pulsed low to indicate that the OnCE serial port is ready toreceive the data to be written; after the data is written, another acknowledge pulse will beprovided.-During hardware reset and when the processor is idle, the DSO pin is held high.
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...I~W:I:0...ffi~0...0...24-BitS6KModuleX MEMORYRAM/ROMEXPANSIONADDRESS ~-I-II-~:::::'--I--I-----L..-I--.-J EXTERNAL wGENERATION ADDRESS 1-4--~UNIT ~r-II-"':"':";=----I----- I--~ BUSo«SWITCHCf)Cf)BUSCONTROL 14--B--_t-«~o0...INTERNALEXTERNALD~A ~.I.'-----I--.II--"II.~----"~"----.T.--~DATABUSSW~HSWITCH ~ ... ~C:(-MODBIIROBMODAIIROARESETDATAALU24X24+56~56-BIT MACTWO 56-BIT ACCUMULATOR_ 16 BITS-24 BITSFigure 10-2 DSP56K Block DiagramDSI/OSO pin is an output when the processor is not in debug mode. When switching fromoutput to input, the pin is three-stated. During hardware reset, this pin is defined as an outputand it is driven low.Note: To avoid possible glitches, an external pull-down resistor should be attached to thispin.