section 7 - Index of
section 7 - Index of section 7 - Index of
10.1 ON-CHIP EMULATION INTRODUCTIONThe DSP56K on-chip emulation (OnCE) circuitry provides a sophisticated debugging toolthat allows simple, inexpensive, and speed independent access to the processor's internalregisters and peripherals. OnCE tells application programmers exactly what the statusis within the registers, memory locations, buses, and even the last five instructions thatwere executed. OnCE capabilities are accessible through a standard set of pins which arethe same on all of the members of the DSP56K processor family. Figure 10-1 shows thecomponents of the OnCE circuitry. OnCE is shown as part of the DSP56K central processingmodule in Figure 10-2.XABYASPASPOB PIL GOB~ + +PipelineInformationJ~ Al' ,.PABFIFOBreakpoint andTrace LogicJ~ A ~~ - ... OnCEControllerandSerialInterfacet j, ,"BreakpointRegistersandComparators- ...OSCKlOS- -..OSI!,?S o-p0os o..Figure 10-1 OnCE Block Diagram10.2 ON-CHIP EMULATION (OnCE) PINSThe following paragraphs describe the OnCE pins associated with the OnCE controllerand serial interface component shown in Figure 10-1.-10.2.1 Debug SerlallnputlChip Status 0 (DSI/OSO)Serial data or commands are provided to the OnCE controller through the DSI/OSO pinwhen it is an input. The data received on the DSI pin will be recognized only when theDSP56K has entered the debug mode of operation. Data is latched on the falling edge ofthe DSCK serial clock (described in Section 10.2.2). Data is always shifted into the OnCEserial port most significant bit (MSB) first. When the DSI/OSO pin is an output, it works inconjunction with the OS1 pin to provide chip status information (see Table 10-1). The
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- Page 144 and 145: interrupts makes it very useful for
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- Page 162 and 163: 7.5 WAIT PROCESSING STATEThe WAIT i
- Page 164 and 165: The stop processing state halts all
- Page 166 and 167: the first instruction fetch). If th
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- Page 184 and 185: cleared. To enable rapid recovery w
- Page 186 and 187: -CLVCCVCC for the CKOUT output. The
- Page 188 and 189: 4. For all input frequencies which
- Page 190 and 191: While the PLL is regaining lock, th
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- Page 198 and 199: 10.3.1.2 Exit Command (EX) Bit 5If
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- Page 204 and 205: To initiate the trace mode of opera
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- Page 210 and 211: The external command controller act
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- Page 219 and 220: 11.1 USER SUPPORTUser support from
- Page 221 and 222: the DSP56K family of processors•
- Page 223 and 224: 11.3.3 Support Integrated Circuits:
- Page 225 and 226: I Document ID I Version Synopsis I
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- Page 233 and 234: 11.12 TRAINING COURSES - (602) 897-
- Page 235 and 236: ADAPTIVE SIGNAL PROCESSINGB. Widrow
- Page 237 and 238: Graphics:CGM AND CGID. B. Arnold an
- Page 239 and 240: NUMERICAL RECIPES IN C - THE ART OF
- Page 241: APPENDIX AINSTRUCTION SET DETAILSAr
10.1 ON-CHIP EMULATION INTRODUCTIONThe DSP56K on-chip emulation (OnCE) circuitry provides a sophisticated debugging toolthat allows simple, inexpensive, and speed independent access to the processor's internalregisters and peripherals. OnCE tells application programmers exactly what the statusis within the registers, memory locations, buses, and even the last five instructions thatwere executed. OnCE capabilities are accessible through a standard set <strong>of</strong> pins which arethe same on all <strong>of</strong> the members <strong>of</strong> the DSP56K processor family. Figure 10-1 shows thecomponents <strong>of</strong> the OnCE circuitry. OnCE is shown as part <strong>of</strong> the DSP56K central processingmodule in Figure 10-2.XABYASPASPOB PIL GOB~ + +PipelineInformationJ~ Al' ,.PABFIFOBreakpoint andTrace LogicJ~ A ~~ - ... OnCEControllerandSerialInterfacet j, ,"BreakpointRegistersandComparators- ...OSCKlOS- -..OSI!,?S o-p0os o..Figure 10-1 OnCE Block Diagram10.2 ON-CHIP EMULATION (OnCE) PINSThe following paragraphs describe the OnCE pins associated with the OnCE controllerand serial interface component shown in Figure 10-1.-10.2.1 Debug SerlallnputlChip Status 0 (DSI/OSO)Serial data or commands are provided to the OnCE controller through the DSI/OSO pinwhen it is an input. The data received on the DSI pin will be recognized only when theDSP56K has entered the debug mode <strong>of</strong> operation. Data is latched on the falling edge <strong>of</strong>the DSCK serial clock (described in Section 10.2.2). Data is always shifted into the OnCEserial port most significant bit (MSB) first. When the DSI/OSO pin is an output, it works inconjunction with the OS1 pin to provide chip status information (see Table 10-1). The