section 7 - Index of

section 7 - Index of section 7 - Index of

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10.1 ON-CHIP EMULATION INTRODUCTIONThe DSP56K on-chip emulation (OnCE) circuitry provides a sophisticated debugging toolthat allows simple, inexpensive, and speed independent access to the processor's internalregisters and peripherals. OnCE tells application programmers exactly what the statusis within the registers, memory locations, buses, and even the last five instructions thatwere executed. OnCE capabilities are accessible through a standard set of pins which arethe same on all of the members of the DSP56K processor family. Figure 10-1 shows thecomponents of the OnCE circuitry. OnCE is shown as part of the DSP56K central processingmodule in Figure 10-2.XABYASPASPOB PIL GOB~ + +PipelineInformationJ~ Al' ,.PABFIFOBreakpoint andTrace LogicJ~ A ~~ - ... OnCEControllerandSerialInterfacet j, ,"BreakpointRegistersandComparators- ...OSCKlOS- -..OSI!,?S o-p0os o..Figure 10-1 OnCE Block Diagram10.2 ON-CHIP EMULATION (OnCE) PINSThe following paragraphs describe the OnCE pins associated with the OnCE controllerand serial interface component shown in Figure 10-1.-10.2.1 Debug SerlallnputlChip Status 0 (DSI/OSO)Serial data or commands are provided to the OnCE controller through the DSI/OSO pinwhen it is an input. The data received on the DSI pin will be recognized only when theDSP56K has entered the debug mode of operation. Data is latched on the falling edge ofthe DSCK serial clock (described in Section 10.2.2). Data is always shifted into the OnCEserial port most significant bit (MSB) first. When the DSI/OSO pin is an output, it works inconjunction with the OS1 pin to provide chip status information (see Table 10-1). The

10.1 ON-CHIP EMULATION INTRODUCTIONThe DSP56K on-chip emulation (OnCE) circuitry provides a sophisticated debugging toolthat allows simple, inexpensive, and speed independent access to the processor's internalregisters and peripherals. OnCE tells application programmers exactly what the statusis within the registers, memory locations, buses, and even the last five instructions thatwere executed. OnCE capabilities are accessible through a standard set <strong>of</strong> pins which arethe same on all <strong>of</strong> the members <strong>of</strong> the DSP56K processor family. Figure 10-1 shows thecomponents <strong>of</strong> the OnCE circuitry. OnCE is shown as part <strong>of</strong> the DSP56K central processingmodule in Figure 10-2.XABYASPASPOB PIL GOB~ + +PipelineInformationJ~ Al' ,.PABFIFOBreakpoint andTrace LogicJ~ A ~~ - ... OnCEControllerandSerialInterfacet j, ,"BreakpointRegistersandComparators- ...OSCKlOS- -..OSI!,?S o-p0os o..Figure 10-1 OnCE Block Diagram10.2 ON-CHIP EMULATION (OnCE) PINSThe following paragraphs describe the OnCE pins associated with the OnCE controllerand serial interface component shown in Figure 10-1.-10.2.1 Debug SerlallnputlChip Status 0 (DSI/OSO)Serial data or commands are provided to the OnCE controller through the DSI/OSO pinwhen it is an input. The data received on the DSI pin will be recognized only when theDSP56K has entered the debug mode <strong>of</strong> operation. Data is latched on the falling edge <strong>of</strong>the DSCK serial clock (described in Section 10.2.2). Data is always shifted into the OnCEserial port most significant bit (MSB) first. When the DSI/OSO pin is an output, it works inconjunction with the OS1 pin to provide chip status information (see Table 10-1). The

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