section 7 - Index of
section 7 - Index of section 7 - Index of
-CLVCCVCC for the CKOUT output. The voltage should be well regulated and the pinshould be provided with an extremely low impedance path to the VCC powerrail. CLVCC should be bypassed to CLGND by a 0.1JlF capacitor located asclose as possible to the chip package.CLGND GND for the CKOUT output. The pin should be provided with an extremely lowimpedance path to ground. CLVCC should be bypassed to CLGND by a 0.1 JlFcapacitor located as close as possible to the chip package.PCAPOff-chip capacitor for the PLL filter. One terminal of the capacitor is connectedto PCAP while the other terminal is connected to PVCC. The capacitor value isspecified in the particular device's Technical Data Sheet.CKOUT This output pin provides a 50% duty cycle output clock synchronized to theinternal processor clock when the PLL is enabled and locked. When the PLL isdisabled, the output clock at CKOUT is derived from, and has the samefrequency and duty cycle as, EXT AL.CKPPINITNote: If the PLL is enabled and the multiplication factor is less than or equal to4, then CKOUT is synchronized to EXTAL.This input pin defines the polarity of the CKOUT signal. Strapping CKP througha resistor to GND will make the CKOUT polarity the same as the EXTALpolarity. Strapping CKP through a resistor to VCC will make the CKOUT polaritythe inverse of the EXTAL polarity. The CKOUT clock polarity is internallylatched at the end of the hardware reset, so that any changes of the CKP pinlogic state after deassertion of RESET will not affect the CKOUT clock polarity.During the assertion of hardware reset, the value at the PINIT input pin iswritten into the PEN bit of the PLL control register. After hardware reset isdeasserted, the PINIT pin is ignored.PLOCK The PLOCK output originates from the Phase Detector. The chip assertsPLOCK when the PLL is enabled and has locked on the proper phase andfrequency of EXTAL. The PLOCK output is deasserted by the chip if the PLL isenabled and has not locked on the proper phase and frequency. PLOCK isasserted if the PLL is disabled. PLOCK is a reliable indicator of the PLL lockstate only after exiting the hardware reset state.
9.4 PLL OPERATION CONSIDERATIONSThe following paragraphs discuss PLL operation considerations.9.4.1 Operating FrequencyThe operating frequency of the chip is governed by the frequency control bits in the PLLcontrol register as follows:F EXT X MFFvcoF CHIP = D F - ----oFwhere:DF is the division factor defined by the DFO-DF3 bitsFCHIP is the chip operating frequencyFEXT is the external input frequency to the chip at the EXTAL pinFvco is the output frequency of the VCOMF is the multiplication factor defined by the MFO-MF11 bitsThe chip frequency is derived from the output of the low power divider. If the lowpower divider is bypassed, the equation is the same but the division factorshould be assumed to be equal to one.9.4.2 Hardware Reset .Hardware reset causes the initialization of the PLL. The following considerations apply:1. The MFO-MF11 bits in the PCTL register are set to their pre-determined hardwarereset value. The DFO-DF3 bits and the Chip Clock Source bit in the PCTLregister are cleared. This causes the chip clock frequency to be equal to theexternal input frequency (EXTAL) multiplied by the multiplication factor definedby MFO-MF11.2. During hardware reset assertion, the PINIT pin value is written into the PENbit in the PCTL register. If the PINIT pin is asserted (setting PEN), the PLLacquires the proper phase/frequency. While hardware reset is asserted, theinternal chip clock will be driven by the EXTAL pin until the PLL achieves lock(if enabled). If the PINIT pin is deasserted during hardware reset assertion, thePEN bit is cleared, the PLL is deactivated and the internal chip clock is drivenby the EXTAL pin.-3. PLOCK is a reliable indicator of the PLL lock state only after exiting the hardwarereset state.
- Page 136 and 137: SP and SSH/SSL register manipulatio
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- Page 140 and 141: Table 7-2 Status Register Interrupt
- Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
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- Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
- Page 148 and 149: 7.3.3.3 Other Interrupt SourcesOthe
- Page 150 and 151: 7.3.4 Interrupt ArbitrationInterrup
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- Page 156 and 157: MAINPROGRAMFETCHESINTERRUPTSYNCHRON
- Page 158 and 159: MAINPROGRAMFAST INTERRUPTVECTORLONG
- Page 160 and 161: MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
- Page 162 and 163: 7.5 WAIT PROCESSING STATEThe WAIT i
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- Page 184 and 185: cleared. To enable rapid recovery w
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- Page 201 and 202: 10.3.4.4 Software Debug Occurrence
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- Page 205 and 206: 10.6.1 External Debug Request Durin
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- Page 209 and 210: are serially available to the exter
- Page 211 and 212: k. ACKI. ClKm. Send command READ FI
- Page 213 and 214: 19. ACK20. Send command READ GDB RE
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- Page 217: SECTION 11ADDITIONAL SUPPORTDr. BuB
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- Page 232 and 233: 11.5 MOTOROLA DSP NEWSThe Motorola
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-CLVCCVCC for the CKOUT output. The voltage should be well regulated and the pinshould be provided with an extremely low impedance path to the VCC powerrail. CLVCC should be bypassed to CLGND by a 0.1JlF capacitor located asclose as possible to the chip package.CLGND GND for the CKOUT output. The pin should be provided with an extremely lowimpedance path to ground. CLVCC should be bypassed to CLGND by a 0.1 JlFcapacitor located as close as possible to the chip package.PCAPOff-chip capacitor for the PLL filter. One terminal <strong>of</strong> the capacitor is connectedto PCAP while the other terminal is connected to PVCC. The capacitor value isspecified in the particular device's Technical Data Sheet.CKOUT This output pin provides a 50% duty cycle output clock synchronized to theinternal processor clock when the PLL is enabled and locked. When the PLL isdisabled, the output clock at CKOUT is derived from, and has the samefrequency and duty cycle as, EXT AL.CKPPINITNote: If the PLL is enabled and the multiplication factor is less than or equal to4, then CKOUT is synchronized to EXTAL.This input pin defines the polarity <strong>of</strong> the CKOUT signal. Strapping CKP througha resistor to GND will make the CKOUT polarity the same as the EXTALpolarity. Strapping CKP through a resistor to VCC will make the CKOUT polaritythe inverse <strong>of</strong> the EXTAL polarity. The CKOUT clock polarity is internallylatched at the end <strong>of</strong> the hardware reset, so that any changes <strong>of</strong> the CKP pinlogic state after deassertion <strong>of</strong> RESET will not affect the CKOUT clock polarity.During the assertion <strong>of</strong> hardware reset, the value at the PINIT input pin iswritten into the PEN bit <strong>of</strong> the PLL control register. After hardware reset isdeasserted, the PINIT pin is ignored.PLOCK The PLOCK output originates from the Phase Detector. The chip assertsPLOCK when the PLL is enabled and has locked on the proper phase andfrequency <strong>of</strong> EXTAL. The PLOCK output is deasserted by the chip if the PLL isenabled and has not locked on the proper phase and frequency. PLOCK isasserted if the PLL is disabled. PLOCK is a reliable indicator <strong>of</strong> the PLL lockstate only after exiting the hardware reset state.
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