section 7 - Index of
section 7 - Index of section 7 - Index of
cleared. To enable rapid recovery when exiting the STOP state, at the cost of higherpower consumption in the STOP state, PSTP should be set. PSTP is cleared by hardwarereset.9.2.5.5 PCTL PLL Enable Bit (PEN) - Bit 18The PEN bit enables the PLL operation. When this bit is set, the PLL is enabled and theinternal clocks will be derived from the PLL VCO output. When this bit is cleared, the PLLis disabled and the internal clocks are derived directly from the clock connected to theEXTAL pin. When the PLL is disabled, the VCO does not operate in order to minimizepower consumption. The PLOCK pin is asserted when PEN is cleared. The PEN bit maybe set by software but it cannot be reset by software. During hardware reset this bitreceives the value of the PINIT pin. The only way to clear PEN is to hold the PINIT pinlow during hardware reset.A relationship exists between PSTP and PEN where PEN adjusts PSTP's control of thePLL o!'>eration. When PSTP is set and PEN (see Table 9-3) is cleared, the on-chip crystaloscillator remains operating in the STOP state, but the PLL is disabled. This powersaving feature enables rapid recovery from the STOP state when the user operates thechip with an on-chip oscillator and with the PLL disabled.Table 9-3 PSTP and PEN RelationshipOperation during STOP-PSTP PEN PLL Oscillator Recovery Power Consumption0 x Disabled Disabled long minimal1 0 Disabled Enabled rapid lower1 1 Enabled Enabled rapid higher9.2.5.6 PCTL Clock Output Disable Bits (CODO-COD1) - Bits 19-20The CODO-COD1 bits control the output buffer of the clock at the CKOUT pin. Table 9-4specifies the effect of CODO-COD1 on the CKOUT pin. When both CODO and COD1 areset, the CKOUT pin is held in the high ("1 ") state. If the CKOUT pin is not connected toexternal Circuits, it is recommended that both COD1 and CODO be set (disabling clockoutput) to minimize RFI noise and power dissipation. If the CKOUT output is low at themoment the CODO-COD1 bits are set, it will complete the low cycle and then be disabledhigh. If the programmer re-enables the CKOUT output before it reaches the high logiclevel during the disabling process, the CKOUT operation will be unaffected. The CODO-COD1 bits are cleared by hardware reset.
Table 9-4 Clock Output Disable Bits CODO-COD1COOl CODa CKOUTPin0 0 Clock Out Enabled, Full Strength Output Buffer0 1 Clock Out Enabled, 2/3 Strength Output Buffer1 0 Clock Out Enabled, 1/3 Strength Output Buffer1 1 Clock Out Disabled9.2.5.7 PCTL Chip Clock Source Bit (CSRC) - Bit 21The CSRC bit specifies whether the clock for the chip is taken from the output of the VCOor is taken from the output of the Low Power Divider (LPD). When CSRC is set, the clockfor the chip is taken from the VCO. When CSRC is cleared, the clock for the chip is takenfrom the output of the LPD. See Section 9.4.8 fo( restrictions. CSRC is cleared by hardwarereset.9.2.5.8 PCTL CKOUT Clock Source Bit (CKOS) - Bit 22The CKOS bit specifies whether the CKOUT clock output is taken from the output of theVCO or is taken from the output of the Low Power Divider (LPD). When CKOS is set, theCKOUT clock output is taken from the VCO. When eKOS is cleared, the CKOUT clockoutput is taken from the output of the LPD. If the PLL is disabled (PEN=O), CKOUT is takenfrom EXT AL. See Section 9.4.8 for restrictions. CKOS is cleared by hardware reset.9.2.5.9 PCTL Reserved Bit - Bit 23This bit is reserved for future expansion. It reads as zero and should be written with zerofor future compatibility.9.3 PLL PINSSome of the PLL pins need not be implemented. The specific PLL pin configuration foreach DSP56K chip implementation is available in the respective device's user's manual.The following pins are dedicated to the PLL operation:-PVCCPGNDvec dedicated to the analog PLL circuits. The voltage should be well regulatedand the pin should be provided with an extremely low impedance path to theVCC power rail. pvce should be bypassed to PGND by a 0.1 JlF capacitorlocated as close as possible to the chip package.GND dedicated to the analog PLL circuits. The pin should be provided with anextremely low impedance path to ground. pvee should be bypassed to PGNDby a 0.1 JlF capacitor located as close as possible to the chip package.
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cleared. To enable rapid recovery when exiting the STOP state, at the cost <strong>of</strong> higherpower consumption in the STOP state, PSTP should be set. PSTP is cleared by hardwarereset.9.2.5.5 PCTL PLL Enable Bit (PEN) - Bit 18The PEN bit enables the PLL operation. When this bit is set, the PLL is enabled and theinternal clocks will be derived from the PLL VCO output. When this bit is cleared, the PLLis disabled and the internal clocks are derived directly from the clock connected to theEXTAL pin. When the PLL is disabled, the VCO does not operate in order to minimizepower consumption. The PLOCK pin is asserted when PEN is cleared. The PEN bit maybe set by s<strong>of</strong>tware but it cannot be reset by s<strong>of</strong>tware. During hardware reset this bitreceives the value <strong>of</strong> the PINIT pin. The only way to clear PEN is to hold the PINIT pinlow during hardware reset.A relationship exists between PSTP and PEN where PEN adjusts PSTP's control <strong>of</strong> thePLL o!'>eration. When PSTP is set and PEN (see Table 9-3) is cleared, the on-chip crystaloscillator remains operating in the STOP state, but the PLL is disabled. This powersaving feature enables rapid recovery from the STOP state when the user operates thechip with an on-chip oscillator and with the PLL disabled.Table 9-3 PSTP and PEN RelationshipOperation during STOP-PSTP PEN PLL Oscillator Recovery Power Consumption0 x Disabled Disabled long minimal1 0 Disabled Enabled rapid lower1 1 Enabled Enabled rapid higher9.2.5.6 PCTL Clock Output Disable Bits (CODO-COD1) - Bits 19-20The CODO-COD1 bits control the output buffer <strong>of</strong> the clock at the CKOUT pin. Table 9-4specifies the effect <strong>of</strong> CODO-COD1 on the CKOUT pin. When both CODO and COD1 areset, the CKOUT pin is held in the high ("1 ") state. If the CKOUT pin is not connected toexternal Circuits, it is recommended that both COD1 and CODO be set (disabling clockoutput) to minimize RFI noise and power dissipation. If the CKOUT output is low at themoment the CODO-COD1 bits are set, it will complete the low cycle and then be disabledhigh. If the programmer re-enables the CKOUT output before it reaches the high logiclevel during the disabling process, the CKOUT operation will be unaffected. The CODO-COD1 bits are cleared by hardware reset.
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