section 7 - Index of

8.2.2.1 Address (AO-A15)These three-state output pins specify the address for external program and data memoryaccesses. To minimize power dissipation, AO-A 15 do not change state when externalmemory spaces are not being accessed.8.2.2.2 Data (00-023)These pins provide the bidirectional data bus for external program and data memory accesses.00-023 are in the high-impedance state when the bus grant signal is asserted.8.2.3 Port A Bus Control SignalsThe following paragraphs describe the Port A bus control signals. The bus control signalsprovide the means to connect additional bus masters (which may be additional OSPs, microprocessors,direct memory access (OMA) controllers, etc.) to the port A bus. They arethree-stated during reset and may require pullup resistors to prevent erroneous operation.8.2.3.1 Read Enable (RD)This three-state output is asserted to read external memory on the data bus (00-023).8.2.3.2 Write Enable (WR)This three-state output is asserted to write external memory on the data bus (00-023).8.2.3.3 Port A Access Control SignalsPort A features a group of configurable pins that perform bus arbitration and bus accesscontrol. The pins, such as Bus Needed (BN), Bus Request. (BR), Bus Grant (BG), BusWait (WT), and Bus Strobe (BS), and their designations differ between members of theOSP56K family and are explained in the respective devices' user manuals.8.2.4 Interrupt and Mode ControlPort A features a pin set that selects the chip's operating mode and receives interrupt requestsfrom external sources. The pins and their designations vary between members ofthe OSP56K family and are explained in the respective devices' user manuals~8.2.5 Port A Wait StatesThe OSP56K processor features two methods to allow the user to accommodate slowmemory by changing the port A bus timing. The first method uses the16-bit bus controlregister (BCR), which resides in X Oata memory space. The BCR allows a fixed numberof wait states to be inserted in a given memory access to all locations in anyone of thefour memory spaces: X, Y, P, and 1/0. The second method uses the bus strobelwait (BSI